| Patent Number |
Title Of Patent |
Date Issued |
| 7611928 |
Method for producing a substrate |
November 3, 2009 |
| Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different |
| 7598543 |
Semiconductor memory component with body region of memory cell having a depression and a graded |
October 6, 2009 |
| A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depre |
| 7528425 |
Semiconductor memory with charge-trapping stack arrangement |
May 5, 2009 |
| A semiconductor memory having a multitude of memory cells (21-1), the semiconductor memory having a substrate (1), at least one wordline (5-1), a first (15-1) and a second line (15-2; 16-1), wherein each of the multitude of memory cells (21-1) comprises a first doping region (6) disp |
| 7385243 |
Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing su |
June 10, 2008 |
| Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regi |
| 7352018 |
Non-volatile memory cells and methods for fabricating non-volatile memory cells |
April 1, 2008 |
| The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacke |
| 7344923 |
NROM semiconductor memory device and fabrication method |
March 18, 2008 |
| An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. |
| 7265424 |
Fin Field-effect transistor and method for producing a fin field effect-transistor |
September 4, 2007 |
| A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain |
| 7208794 |
High-density NROM-FINFET |
April 24, 2007 |
| Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal |
| 7195978 |
Method for the production of a memory cell, memory cell and memory cell arrangement |
March 27, 2007 |
| Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a |
| 7180115 |
DRAM cell structure with tunnel barrier |
February 20, 2007 |
| The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected |
| 7157768 |
Non-volatile flash semiconductor memory and fabrication method |
January 2, 2007 |
| In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the |
| 7154138 |
Transistor-arrangement, method for operating a transistor arrangement as a data storage element |
December 26, 2006 |
| The invention relates to a transistor arrangement having a substrate and a vertical transistor comprising: a first electrode region, a second electrode region arranged essentially above the latter, and, in between, a channel region, and also a gate region beside the channel region and, |
| 6998672 |
Memory cell |
February 14, 2006 |
| A memory cell having a source region, a drain region, a source-end control gate, a drain-end control gate, an injection gate arranged between the source-end control gate and the drain-end control gate, a source-end storage element arranged in the source-end control gate, and a drain-end |
| 6982202 |
Fabrication method for memory cell |
January 3, 2006 |
| Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor la |
| 6979859 |
Flash memory cell and fabrication method |
December 27, 2005 |
| Memory cells, formed as trench transistors, having a respective floating gate electrode and a control gate electrode at a trench wall above a channel region between doped regions for source and drain are provided with a gate electrode arranged in a further trench, via which gate elec |
| 6977413 |
Bar-type field effect transistor and method for the production thereof |
December 20, 2005 |
| The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar. |
| 6798014 |
Semiconductor memory cell and semiconductor component as well as manufacturing methods therefore |
September 28, 2004 |
| A semiconductor memory cell with a storage transistor, a selection transistor and a layer structure is provided. The layer structure is formed of at least two semiconductor layers separated from one another by a dielectric. A control electrode that controls a current flow through the |
| 6750095 |
Integrated circuit with vertical transistors |
June 15, 2004 |
| A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a |
| 6707098 |
Electronic device and method for fabricating an electronic device |
March 16, 2004 |
| An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied on the layer system. The first and second nanowires are arranged skew with respect to one another. The layer system is set up |
| 6599797 |
SOI DRAM without floating body effect |
July 29, 2003 |
| The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO.sub.2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. |
| 6566182 |
DRAM memory cell for DRAM memory device and method for manufacturing it |
May 20, 2003 |
| A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction between the drain and source regions. |
| 6492221 |
DRAM cell arrangement |
December 10, 2002 |
| A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memory cell of a column. A first word |
| 6352894 |
Method of forming DRAM cell arrangement |
March 5, 2002 |
| A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/dra |
| 6349052 |
DRAM cell arrangement and method for fabricating it |
February 19, 2002 |
| A capacitor of a memory cell is produced in a depression (V) in a first substrate (1). The first substrate (1) is connected to a second substrate (2) in such a way that an insulating layer (I) is arranged between them. The second substrate (2) is thinned. A transistor of the memory cell |
| 6180458 |
Method of producing a memory cell configuration |
January 30, 2001 |
| A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed |
| 6111267 |
CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed |
August 29, 2000 |
| An integrated CMOS circuit, and method for producing same, including a semiconductor substrate having a p-channel MOS transistor and an n-channel MOS transistor formed therein and having a first silicon layer, a stressed Si.sub.1-x Ge.sub.x layer and a second silicon layer which are pref |
| 6049105 |
DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing |
April 11, 2000 |
| A DRAM cell arrangement having dynamic, self-amplifying memory cells, and method for manufacturing same, wherein each memory cell includes a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are each fashioned as verti |
| 6044009 |
DRAM cell arrangement and method for its production |
March 28, 2000 |
| A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/dra |
| 5959328 |
Electrically programmable memory cell arrangement and method for its manufacture |
September 28, 1999 |
| An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on |
| 5882969 |
Method for manufacturing an electrically writeable and erasable read-only memory cell arrangemen |
March 16, 1999 |
| In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS tr |
| 5821591 |
High density read only memory cell configuration and method for its production |
October 13, 1998 |
| A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed |
| 5736761 |
DRAM cell arrangement and method for its manufacture |
April 7, 1998 |
| The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capa |
| 5559353 |
Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture t |
September 24, 1996 |
| A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the |
| 5443992 |
Method for manufacturing an integrated circuit having at least one MOS transistor |
August 22, 1995 |
| An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is provided in the insulating layer. A vertical layer sequence that comprises at least a c |
