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Inventor: Hiraishi; Atsushi
Address: Kodaira, JP
No. of patents: 4
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 6271687 |
Sense amplifier circuit |
August 7, 2001 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 6046609 |
Sense amplifier circuit |
April 4, 2000 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 5963483 |
Synchronous memory unit |
October 5, 1999 |
| A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the |
| 5854562 |
Sense amplifier circuit |
December 29, 1998 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
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