| Patent Number |
Title Of Patent |
Date Issued |
| 6195748 |
Apparatus for sampling instruction execution information in a processor pipeline |
February 27, 2001 |
| An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. E |
| 6163840 |
Method and apparatus for sampling multiple potentially concurrent instructions in a processor pi |
December 19, 2000 |
| An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A |
| 6148396 |
Apparatus for sampling path history in a processor pipeline |
November 14, 2000 |
| An apparatus is provided for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system. The apparatus identifies a class of instructions to be sampled. Path-identifying state information of a current |
| 6119075 |
Method for estimating statistics of properties of interactions processed by a processor pipeline |
September 12, 2000 |
| Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are r |
| 6070009 |
Method for estimating execution rates of program execution paths |
May 30, 2000 |
| A method is provided for estimating execution rates of program executions paths. The method samples path-identifying state information of selected instructions while executing the program in a processor. A control flow graph of the program is supplied, the control flow graph includes a |
| 6000044 |
Apparatus for randomly sampling instructions in a processor pipeline |
December 7, 1999 |
| An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are iden |
| 5964867 |
Method for inserting memory prefetch operations based on measured latencies in a program optimiz |
October 12, 1999 |
| A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are process |
| 5923872 |
Apparatus for sampling instruction operand or result values in a processor pipeline |
July 13, 1999 |
| An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a par |
| 5809450 |
Method for estimating statistics of properties of instructions processed by a processor pipeline |
September 15, 1998 |
| A method is provided for estimating statistics of properties of instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Some of the fetched instructions are randomly |
