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Inventor:
Hewitt; Larry D.
Address:
Austin, TX
No. of patents:
48
Patents:












Patent Number Title Of Patent Date Issued
7986727 In-band method to configure equalization levels July 26, 2011
An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equa
7983181 Technique for negotiating a width of a packet-based communication link July 19, 2011
A technique for negotiating the width of a link between a first device and a second device includes detecting, during initialization, a respective signal on one or more control lines associated with at least a portion of an N-bit link. The N-bit link is configured as a single link ha
7617404 In-band power management in a communication link November 10, 2009
A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more trainin
7607031 Power management in a communication link October 20, 2009
A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training p
7455450 Method and apparatus for temperature sensing in integrated circuits November 25, 2008
A method and apparatus for temperature sensing in an IC. The IC includes a plurality of remote temperature sensors each coupled to a control logic unit. The plurality of remote temperature sensors may be distributed throughout the integrated circuit. The integrated circuit includes a
7451337 Guaranteed edge synchronization for multiple clocks November 11, 2008
A method and apparatus for guaranteeing clock edge synchronization is disclosed. In one embodiment, a system for synchronizing clock signals includes a clock unit and a synchronization unit. Both the clock unit and the synchronization unit may be configured to receive a reference clock
7421525 System including a host connected to a plurality of memory modules via a serial memory interconn September 2, 2008
A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to
7334123 Computer system including a bus bridge for connection to a security services processor February 19, 2008
A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector
7308514 Configuring a communication link interface December 11, 2007
Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes
7231474 Serial interface having a read temperature command June 12, 2007
A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read
7174467 Message based power management in a multi-processor system February 6, 2007
A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the proc
7146510 Use of a signal line to adjust width and/or frequency of a communication link during system oper December 5, 2006
An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency
7051218 Message based power management May 23, 2006
A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power
7000149 External loopback test mode February 14, 2006
A method and apparatus for testing the transmitter and receiver links of an I/O node. A test mode in an I/O node is initiated by a test signal driven from a test system to the I/O node via a loadboard. The I/O node may then receive test data through a peripheral bus interface. The in
6928528 Guaranteed data synchronization August 9, 2005
A method and apparatus for guaranteed data synchronization. In one embodiment, a data synchronization unit includes a memory unit, a write pointer unit, a read pointer unit, and synchronization pulse logic. The memory unit may receive information from a source external to the data sy
6865618 System and method of assigning device numbers to I/O nodes of a computer system March 8, 2005
A system and method of assigning device numbers to a plurality of I/O nodes of a computer system. Each of the plurality of input/output nodes is initialized to a common default device number. The method includes assigning a unique device number such as a Unit ID, for example, to each
6862647 System and method for analyzing bus transactions March 1, 2005
A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second
6857033 I/O node for a computer system including an integrated graphics engine and an integrated I/O hub February 15, 2005
An I/O node for a computer system including an integrated graphics engine and integrated I/O hub. An input/output node that is implemented on an integrated circuit chip includes a transceiver unit, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on
6807599 Computer system I/O node for connection serially in a chain to a host October 19, 2004
A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter unit coupled to transmit a first corresponding command that corresponds to the first command o
6791554 I/O node for a computer system including an integrated graphics engine September 14, 2004
An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The firs
6725297 Peripheral interface circuit for an I/O node of a computer system April 20, 2004
A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and
6697890 I/O node for a computer system including an integrated I/O interface February 24, 2004
An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The f
6618782 Computer interconnection bus link layer September 9, 2003
A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of second functions via a communication link that includes a plurality of pipes carrying trans
6611891 Computer resource configuration mechanism across a multi-pipe communication link August 26, 2003
Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes
6571332 Method and apparatus for combined transaction reordering and buffer management May 27, 2003
A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality
6557048 Computer system implementing a system and method for ordering input/output (IO) memory operation April 29, 2003
A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected v
6532019 Input/output integrated circuit hub incorporating a RAMDAC March 11, 2003
A computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An I/O hub, which is coupled to a plurality of input/output buses, includes a RAMDAC. An interconnect bus couples the first integrated circuit and the I/O hub and
6385705 Circuit and method for maintaining order of memory access requests initiated by devices in a mul May 7, 2002
A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at lea
6370600 Staging buffer for translating clock domains when source clock frequency exceeds target clock fr April 9, 2002
An apparatus is configured to monitor the source and target clocks (e.g., receive and transmit clocks, respectively, each from different clock domains) to determine if the respective frequencies of the clocks lead to more data being received by a buffer used to communicate between the tw
6272465 Monolithic PC audio circuit August 7, 2001
A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and
6202116 Write only bus with whole and half bus mode operation March 13, 2001
A data bus is divided into two portions. One portion of the bus transfers data from one side of the bus to the other and the other portion of the bus transfers data in the opposite direction. Bus cycles that originate from one side of the bus only go in one direction (from the originator
6199132 Communication link with isochronous and asynchronous priority modes March 6, 2001
A bus transfers information including isochronous and asynchronous data between a first and a second integrated circuit. The bus guarantees a minimum bandwidth to isochronous data and also tries to minimize latency for isochronous data. The bus transfers data in asynchronous priority mod
6167492 Circuit and method for maintaining order of memory access requests initiated by devices coupled December 26, 2000
A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at lea
6148357 Integrated CPU and memory controller utilizing a communication link having isochronous and async November 14, 2000
An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a
6058066 Enhanced register array accessible by both a system microprocessor and a wavetable audio synthes May 2, 2000
A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port
5987541 Computer system using signal modulation techniques to enhance multimedia device communication November 16, 1999
A computer system is presented having various devices capable of exchanging data using either binary data signals or a.c. signals created by carrier waveform modulation. The computer system includes a common bus having a signal bandwidth divided up to form two or more separate communicat
5956493 Bus arbiter including programmable request latency counters for varying arbitration priority September 21, 1999
A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for
5918073 System and method for equalizing data buffer storage and fetch rates of peripheral devices June 29, 1999
A system and method are presented for equalizing data buffer storage and fetch rates of peripheral devices. A computer system of the present invention includes a central processing unit (CPU), first and second peripheral devices, and a data buffer. The first peripheral device stores
5898886 Multimedia devices in computer system that selectively employ a communications protocol by deter April 27, 1999
A computer system is presented having various peripheral devices coupled to a PCI local bus (i.e., an expansion bus), a subset of the peripheral devices having quaternary interfaces configured to communicate via quaternary signals conveyed upon the PCI local bus. The various peripheral
5859995 Method and apparatus for coordinating combinatorial logic-clocked state machines January 12, 1999
A triggering circuit obviates propagation differences in differential combinatorial logic clocking of upstream and downstream state machines ("SM's"). The triggering circuit imposes an output state on the downstream SM in response to the appearance of an appropriate combination of the
5847304 PC audio system with frequency compensated wavetable data December 8, 1998
The PC audio circuit described interfaces with and provides audio enhancement to a host personal computer of the type including a central processor, system memory and a system bus. The PC audio circuit includes a digital signal processor (DSP) for processing wavetable data and genera
5809466 Audio processing chip with external serial port September 15, 1998
This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data dev
5794021 Variable frequency clock generation circuit using aperiodic patterns August 11, 1998
A method and circuit for generating a selectively variable clock signal from one of 256 frequencies within a specified range from two fixed frequency oscillator source signals is provided. The method and circuitry maintain a substantially fifty-percent duty cycle in the output clock
5753841 PC audio system with wavetable cache May 19, 1998
The PC audio circuit described interfaces with and provides audio enhancement to a host personal computer of the type including a central processor, system memory and a system bus. The PC audio circuit includes a digital signal processor (DSP) for processing wavetable data and genera
5675808 Power control of circuit modules within an integrated circuit October 7, 1997
A power control and memory refresh rate management circuit is described. The power control circuit provides circuitry for selectively disabling or enabling modular logic circuit blocks within a VLSI integrated circuit under program control from an external processor, or for suspended cir
5668338 Wavetable audio synthesizer with low frequency oscillators for tremolo and vibrato effects September 16, 1997
A digital wavetable audio synthesizer with an LFO generator is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects. The synthesizer includes an address generator which has several modes of addressing wavetable data.
5659466 Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer August 19, 1997
A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer
5546039 Charge dissipation in capacitively loaded ports August 13, 1996
A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clock










 
 
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