| Patent Number |
Title Of Patent |
Date Issued |
| 6205560 |
Debug system allowing programmable selection of alternate debug mechanisms such as debug handler |
March 20, 2001 |
| A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the st |
| 6138230 |
Processor with multiple execution pipelines using pipe stage state information to control indepe |
October 24, 2000 |
| A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions |
| 6073231 |
Pipelined processor with microcontrol of register translation hardware |
June 6, 2000 |
| A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated wi |
| 5961575 |
Microprocessor having combined shift and rotate circuit |
October 5, 1999 |
| Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following sequence: an 8-bit shift and rotate circuit, a 16-bit shift and rotate circuit, a 1-bit shift |
| 5838897 |
Debugging a processor using data output during idle bus cycles |
November 17, 1998 |
| A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality |
| 5835949 |
Method of identifying and self-modifying code |
November 10, 1998 |
| A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction |
| 5805879 |
In a pipelined processor, setting a segment access indicator during execution stage using except |
September 8, 1998 |
| In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circu |
| 5794026 |
Microprocessor having expedited execution of condition dependent instructions |
August 11, 1998 |
| A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is rec |
| 5742755 |
Error-handling circuit and method for memory address alignment double fault |
April 21, 1998 |
| In an .chi.86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest privilege level and executable in the processor to cause the processor to calculate addr |
| 5644741 |
Processor with single clock decode architecture employing single microROM |
July 1, 1997 |
| A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memor |
| 5596735 |
Circuit and method for addressing segment descriptor tables |
January 21, 1997 |
| In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local base address registers alternative |
| 5524222 |
Microsequencer allowing a sequence of conditional jumps without requiring the insertion of NOP o |
June 4, 1996 |
| A sequencer for use in a pipeline architecture includes circuitry for determining whether the previous instruction was a conditional jump instruction and whether the condition was met, circuitry for determining whether the current instruction is a conditional jump, and circuitry inhi |
| 5471598 |
Data dependency detection and handling in a microprocessor with write buffer |
November 28, 1995 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
