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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Herr; Quentin P.
Address:
Torrance, CA
No. of patents:
20
Patents:












Patent Number Title Of Patent Date Issued
7170960 Instantaneous clock recovery circuit January 30, 2007
A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to
6917216 Superconductor output amplifier July 12, 2005
A single flux quantum (SFQ) pulse is generated (502) by injecting a superconductor output signal as a first signal at a "start" input (108) coupled to a superconductor delay element (104). The SFQ pulse is reflected (504) back and forth between first and second superconductor reflect
6909109 Superconducting digital first-in first-out buffer using physical back pressure mechanism June 21, 2005
A digital first-in first-out (FIFO) buffer (10) for use with Single Flux Quantum (SFQ) superconductive integrated circuits. The digital FIFO buffer (10) includes a clock-storage circuit (14) for receiving and storing load and read clock signals (100, 104) and a data-storage circuit (16)
6865639 Scalable self-routing superconductor switch March 8, 2005
A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data i
6836141 Superconductor ballistic RAM December 28, 2004
A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junc
6777808 Capacitor for signal propagation across ground plane boundaries in superconductor integrated cir August 17, 2004
The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads,
6759974 Encoder and decoder for data transfer in superconductor circuits July 6, 2004
A decoder for decoding data transmitted between superconductor circuits. Interleaved data and clock pulses are applied to a clock input of a flip-flop circuit and one input of an AND gate. The output of the flip-flop circuit is a clock signal, and is applied to a delay circuit to be
6750794 Application of single flux quantum pulse interaction to the simultaneous sampling in-phase and q June 15, 2004
A superconducting oscillator/counter analog-to-digital converter (50) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator (12). A clock circuit
6734699 Self-clocked complementary logic May 11, 2004
A superconducting self-clocked complementary SFQ logic family. The basic element of the circuit is a plurality of Josephson junctions and a control inductance coupled across a pair of voltage rails. An important aspect of the invention relates to the use of voltage biasing for the Joseph
6678540 Transmission line single flux quantum chip-to -chip communication with flip-chip bump transition January 13, 2004
A superconductor on-chip microstrip line (2, 4) to off-chip microstrip line (7) transition of low characteristic impedance (15, 20, 22) is realized that obtains a bandwidth of 200 GHz for MCM application while employing solder bump (15, 17) technology to connect the chips (3, 5) to the
6580310 Double flux quantum superconductor driver June 17, 2003
A rapid SFQ one-way buffer (13, 1, 4, 5, 15, 2 & 9), is combined with a Josephson transmission line (17,3, 19, 16, 21 & 4) that is lightly loaded (R.sub.L) to provide a superconductor driver capable of producing double flux quantum output pulses. Each SFQ pulse applied to the input of th
6518786 Combinational logic using asynchronous single-flux quantum gates February 11, 2003
An asynchronous SFQ logic cell that is amenable to being used in combinational logic circuits. Rather than encode each digital logic bit as one SFQ pulse, each logic bit is encoded as a series of SFQ pulses. As such, merge and join circuits can be used for elementary logic cells to f
6518673 Capacitor for signal propagation across ground plane boundaries in superconductor integrated cir February 11, 2003
The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads,
6507234 Active timing arbitration in superconductor digital circuits January 14, 2003
A superconductor circuit (50) for providing active timing arbitration between SFQ pulses. The superconductor circuit (50) includes a first superconducting transmission line (52) having at least one inductor (54) for transmitting first input pulses, and a second superconducting transm
6483339 Single flux quantum series biasing technique using superconducting DC transformer November 19, 2002
The level of bias current (12) required by a superconductor integrated circuit (2 & 4) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion (2) in one ground plane in series (10) with that for the circuit
6452520 Gated counter analog-to-digital converter with error correction September 17, 2002
A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generat
6420895 High-sensitivity, self-clocked receiver for multi-chip superconductor circuits July 16, 2002
A receiver (50) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver (50) includes a detector circuit (52) for asynchronously receiving an input current, a splitter circuit (60) connected to the detector circuit (52) for generating first and s
6229332 Superconductive logic gate and random access memory May 8, 2001
The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N),
6154044 Superconductive logic gate and random access memory November 28, 2000
The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N) e
6078517 Superconducting memory cell with directly-coupled readout June 20, 2000
A superconducting cell (10) is provided which has a storage loop (12), a read-out loop (14), and a direct coupling element between the storage loop (12) and read-out loop (14). The direct coupling element is preferably an inductor (30) common to the storage loop (12) and read-out loop (1










 
 
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