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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Her; Tzong-Dar
Address:
Taichung, TW
No. of patents:
10
Patents:




Patent Number Title Of Patent Date Issued
6731015 Super low profile package with stacked dies May 4, 2004
A super low profile package with stacked dies comprises a substrate, a heat spreader, a first die, a second die, a molding compound, and a number of solder balls. The substrate has a cavity, a top surface and a bottom surface opposite to the top surface. The heat spreader is connected to
6713321 Super low profile package with high efficiency of heat dissipation March 30, 2004
A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink
6650009 Structure of a multi chip module having stacked chips November 18, 2003
A structure of a multi chip module package having stacked chips, having at least a substrate, a main chip, a plurality of chip sets, a plurality of spacers, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposit
6593662 Stacked-die package structure July 15, 2003
A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by
6583499 Quad flat non-leaded package and leadframe for use in a quad flat non-leaded package June 24, 2003
A quad flat non-leaded package comprises: a die pad having a first upper surface and a corresponding first lower surface thereon a plurality of interlacing slots are formed, each of the interlacing slots extending to the edges of the die pad to form a plurality of island-like blocks; a
6541854 Super low profile package with high efficiency of heat dissipation April 1, 2003
A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink
6525942 Heat dissipation ball grid array package February 25, 2003
A heat dissipation ball grid array package includes the following elements. A plurality of first thermal ball pads is formed on the underside of a substrate in the area covered by chip. A plurality of second thermal ball pads or a heat dissipation ring is formed outside the first thermal
6392425 Multi-chip packaging having non-sticking test structure May 21, 2002
A multi-chip packaging substrate having a non-sticking test structure consists of a plurality of non-sticking test spots formed in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an
6391666 Method for identifying defective elements in array molding of semiconductor packaging May 21, 2002
The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites dispose
6218731 Tiny ball grid array package April 17, 2001
A tiny ball grid array package based on a substrate. The substrate has at least an insulation layer and two copper foils laminated together. A hole is formed near the center of the substrate. A second one of the copper foils is patterned into multiple conductive traces formed on a surfac


 
 
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