| Patent Number |
Title Of Patent |
Date Issued |
| 5302952 |
Automatic A/D converter operation with pause capability |
April 12, 1994 |
| An analog-to-digital conversion module, QADC (1), and method minimize software involvement by providing a pause capacility. Each queue in the QADC (1) has one or more Conversion Command Words, CCWs (82), in a Conversion Command Word Table (62). Each conversion command word, CCW (82), |
| 5263168 |
Circuitry for automatically entering and terminating an initialization mode in a data processing |
November 16, 1993 |
| A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) should execute an initialization |
| 5168276 |
Automatic A/D converter operation using a programmable control table |
December 1, 1992 |
| An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, |
| 5138709 |
Spurious interrupt monitor |
August 11, 1992 |
| In a microprocessor system including arbitration for an interrupt, an apparatus and method for monitoring the arbitration lines to determine whether an interrupt request is real or spurious is includued. Once an interrupt acknowledge signal is provided, the interrupting apparatus must |
| 5081454 |
Automatic A/D converter operation using programmable sample time |
January 14, 1992 |
| An analog-to-digital conversion system module and method provides programmable times for sampling analog input signals. Software involvement is minimized by providing a command word which includes information specifying a sample time. The command word may be stored in a register or m |
| 4958277 |
Queued serial peripheral interface for use in a data processing system |
September 18, 1990 |
| A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling d |
| 4816996 |
Queued serial peripheral interface for use in a data processing system |
March 28, 1989 |
| A serial peripheral interface achieves compatibility with devices having previous such interfaces while significantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling d |
| 4802119 |
Single chip microcomputer with patching and configuration controlled by on-board non-volatile me |
January 31, 1989 |
| A single chip microcomputer with patching and configuration is provided with blocks of patch memory which may be patched over faulty and/or obsolete areas of the microcomputer's memory map under control of starting address registers which are implemented in on-board non-volatile memory. |
