| Patent Number |
Title Of Patent |
Date Issued |
| 7573103 |
Back-to-back NPN/PNP protection diodes |
August 11, 2009 |
| A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and elec |
| 7561471 |
Cycling improvement using higher erase bias |
July 14, 2009 |
| Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cell |
| 7561457 |
Select transistor using buried bit line from core |
July 14, 2009 |
| A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in t |
| 7553727 |
Using implanted poly-1 to improve charging protection in dual-poly process |
June 30, 2009 |
| The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the |
| 7402868 |
System and method for protecting semiconductor devices |
July 22, 2008 |
| A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device. |
| 7319615 |
Ramp gate erase for dual bit flash memory |
January 15, 2008 |
| A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value tha |
| 7285827 |
Back-to-back NPN/PNP protection diodes |
October 23, 2007 |
| A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device. |
| 7269067 |
Programming a memory device |
September 11, 2007 |
| A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias |
| 7215577 |
Flash memory cell and methods for programming and erasing |
May 8, 2007 |
| Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electron |
| 7170796 |
Methods and systems for reducing the threshold voltage distribution following a memory cell eras |
January 30, 2007 |
| A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold |
| 7167398 |
System and method for erasing a memory cell |
January 23, 2007 |
| A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and era |
| 7157335 |
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact r |
January 2, 2007 |
| The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of |
| 7120063 |
Flash memory cell and methods for programming and erasing |
October 10, 2006 |
| Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electron |
| 6958272 |
Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memor |
October 25, 2005 |
| A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a p |
| 6934190 |
Ramp source hot-hole programming for trap based non-volatile memory devices |
August 23, 2005 |
| Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths |
| 6834012 |
Memory device and methods of using negative gate stress to correct over-erased memory cells |
December 21, 2004 |
| Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold volta |
| 6795357 |
Method for reading a non-volatile memory cell |
September 21, 2004 |
| A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain volt |
| 6795342 |
System for programming a non-volatile memory cell |
September 21, 2004 |
| A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is t |
| 6788583 |
Pre-charge method for reading a non-volatile memory cell |
September 7, 2004 |
| A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage |
| 6771545 |
Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile m |
August 3, 2004 |
| An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a |
| 6768673 |
Method of programming and reading a dual cell memory device |
July 27, 2004 |
| A method of programming and reading a dual cell memory device. The method includes storing a selected program level in each cell and reading one of the cells to determine a single data value stored by the memory device. |
