| Patent Number |
Title Of Patent |
Date Issued |
| 7611924 |
Integrated circuit package with chip-side signal connections |
November 3, 2009 |
| Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure. |
| 7589414 |
I/O Architecture for integrated circuit package |
September 15, 2009 |
| A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive |
| 7564066 |
Multi-chip assembly with optically coupled die |
July 21, 2009 |
| Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least |
| 7554203 |
Electronic assembly with stacked IC's using two or more different connection technologies and me |
June 30, 2009 |
| An integrated circuit ("IC") package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output ("I/O") bandwidth. In an embodiment, one die is a processor and at least one other die is a |
| 7538019 |
Forming compliant contact pads for semiconductor packages |
May 26, 2009 |
| In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, |
| 7535689 |
Reducing input capacitance of high speed integrated circuits |
May 19, 2009 |
| An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad. |
| 7535080 |
Reducing parasitic mutual capacitances |
May 19, 2009 |
| A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes a |
| 7511359 |
Dual die package with high-speed interconnect |
March 31, 2009 |
| Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the first die. A fi |
| 7477197 |
Package level integration of antenna and RF front-end module |
January 13, 2009 |
| Electronic devices and methods for their formation are described. One device relates to an electronic assembly including a substrate having a first surface and a second surface opposite the first surface. The electronic assembly also includes at least one RF front-end module coupled |
| 7432779 |
Transmission line impedance matching |
October 7, 2008 |
| Transmission line impedance matching for matching an impedance discontinuity on a transmission signal trace with one or more non-transmission traces disposed near the transmission signal trace at a region corresponding to the impedance discontinuity. |
| 7432592 |
Integrated micro-channels for 3D through silicon architectures |
October 7, 2008 |
| Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures. |
| 7373033 |
Chip-to-chip optical interconnect |
May 13, 2008 |
| A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optica |
| 7352557 |
Vertical capacitor apparatus, systems, and methods |
April 1, 2008 |
| An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates. |
| 7348678 |
Integrated circuit package to provide high-bandwidth communication among multiple dice |
March 25, 2008 |
| A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is dispose |
| 7348661 |
Array capacitor apparatuses to filter input/output signal |
March 25, 2008 |
| An apparatus for filtering noise from an input/output (I/O) signal is disclosed. In various embodiments, the apparatus may be an array capacitor, and may be disposed between an electronic package and an underlying substrate such as a printed circuit board. |
| 7345359 |
Integrated circuit package with chip-side signal connections |
March 18, 2008 |
| Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure. |
| 7279391 |
Integrated inductors and compliant interconnects for semiconductor packaging |
October 9, 2007 |
| Some embodiments of the present invention include integrated inductors and compliant interconnects for semiconductor packaging. |
| 7255573 |
Data signal interconnection with reduced crosstalk |
August 14, 2007 |
| Data signal interconnections are described that offer reduced cross talk particularly with high speed differential signaling. In one example, the invention includes a plurality of interconnects to carry data signals between a first component and a second component, the plurality of i |
| 7227247 |
IC package with signal land pads |
June 5, 2007 |
| In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the si |
| 7218183 |
Transmission line impedance matching |
May 15, 2007 |
| Transmission line impedance matching for matching an impedance discontinuity on a transmission signal trace with one or more non-transmission traces disposed near the transmission signal trace at a region corresponding to the impedance discontinuity. |
| 7209025 |
Multilayer inductor with shielding plane |
April 24, 2007 |
| Some embodiments provide a first portion of an inductor disposed in a first layer of a multilayer substrate, a second portion of the inductor disposed in a second layer of the multilayer substrate, the second portion coupled to the first portion, and a shielding plane disposed betwee |
| 7205638 |
Silicon building blocks in integrated circuit packaging |
April 17, 2007 |
| An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second mater |
| 7123466 |
Extended thin film capacitor (TFC) |
October 17, 2006 |
| Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package. |
| 7110263 |
Reference slots for signal traces |
September 19, 2006 |
| An apparatus comprises a signal layer including a first and second signal trace. The apparatus also comprises a first reference plane including a first slot substantially parallel to the first and second signal traces. Further, the apparatus includes a dielectric layer having at least a |
| 7027289 |
Extended thin film capacitor (TFC) |
April 11, 2006 |
| Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package. |
| 6885544 |
Vertical capacitor apparatus, systems, and methods |
April 26, 2005 |
| An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates. |
| 6815256 |
Silicon building blocks in integrated circuit packaging |
November 9, 2004 |
| An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second mater |
