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Inventor: Hayes; Jerry D
Address: Mllton, VT
No. of patents: 1
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7444608 |
Method and system for evaluating timing in an integrated circuit |
October 28, 2008 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
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