| Patent Number |
Title Of Patent |
Date Issued |
| 6594785 |
System and method for fault handling and recovery in a multi-processing system having hardware r |
July 15, 2003 |
| Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A |
| 6434641 |
System for reducing the number of requests presented to a main memory in a memory storage system |
August 13, 2002 |
| A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some request |
| 6263409 |
Data processing system and method for substituting one type of request for another for increased |
July 17, 2001 |
| A data processing system and method for substituting selected requests with substitute requests that perform the same or similar end function but achieve increased system performance are disclosed. Those requests that have a selected request characteristic are identified and converted or |
| 6189078 |
System and method for increasing data transfer throughput for cache purge transactions using mul |
February 13, 2001 |
| A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory |
| 6167489 |
System and method for bypassing supervisory memory intervention for data transfers between devic |
December 26, 2000 |
| A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first |
| 5717942 |
Reset for independent partitions within a computer system |
February 10, 1998 |
| A method and apparatus for providing a multi-source reset for independent partitions within a multiprocessor computer system. In a system having at least two partitions wherein the at least two partitions share interconnect hardware, a reset may be provided to a first one of the at l |
| 5625892 |
Dynamic power regulator for controlling memory power consumption |
April 29, 1997 |
| A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of |
| 5423016 |
Block buffer for instruction/operand caches |
June 6, 1995 |
| A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read c |
