Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hau-Riege; Christine
Address:
Fremont, CA
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
7818655 Method for quantitative detection of multiple electromigration failure modes October 19, 2010
According to one exemplary embodiment, a computer implemented method for detecting multiple failure modes in a set of electromigration failure data points includes sorting the data points by time to failure and dividing the data points to form first and second groups of data points t
7451411 Integrated circuit design system November 11, 2008
The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration cri
7026225 Semiconductor component and method for precluding stress-induced void formation in the semicondu April 11, 2006
A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A
6867056 System and method for current-enhanced stress-migration testing of interconnect March 15, 2005
For testing for stress-migration failure of interconnect, an interconnect test structure is formed with a first feeder line coupled to a test line by a first no-flux structure, and with a second feeder line coupled to the test line by a second no-flux structure. A respective width of ea
6822473 Determination of permeability of layer material within interconnect November 23, 2004
Electromigration permeability is determined for a layer material within an interconnect test structure comprised of a feeder line, a test line, and a supply line. A no-flux structure is disposed between the feeder line and the test line, and the layer material is disposed between the tes
6822437 Interconnect test structure with slotted feeder lines to prevent stress-induced voids November 23, 2004
An interconnect test structure for characterizing electromigration includes a test line and a feeder coupled to the test line by a via structure. A width of the feeder line is greater than a width of the test line. Slots are formed in the feeder line for preventing formation of a stress-
6818557 Method of forming SiC capped copper interconnects with reduced hillock formation and improved el November 16, 2004
The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH.sub.3 and N.sub.2, ramping up
6768323 System and method for determining location of extrusion in interconnect July 27, 2004
For locating an extrusion from an interconnect, an extrusion monitor structure is formed to surround the interconnect and is separated from the interconnect by a dielectric material. A first via is coupled to the interconnect, and a second via is coupled to the extrusion monitor stru
6762597 Structure, system, and method for assessing electromigration permeability of layer material with July 13, 2004
For determining electromigration permeability of a layer material, a test line, a feeder line, and a cathode line of an interconnect test structure are formed with current flowing from the test line through the feeder line to the cathode line. A no-flux structure is disposed between the
6725433 Method for assessing the reliability of interconnects April 20, 2004
A methodology for testing interconnect structures includes testing a number of short line interconnects having the same length and different reservoir sizes. By measuring and comparing the stress values on the interconnects, a relationship between reservoir area and jL.sub.crit may be ob
6714037 Methodology for an assessment of the degree of barrier permeability at via bottom during electro March 30, 2004
A system and method is disclosed for determining a barrier permeability at a via. A test structure is formed having a test barrier between two conductors. A substantially constant current is conducted through the test structure to measure the lifetime of the test structure. A barrier










 
 
  Recently Added Patents
System and method for providing definitions
Image processing apparatus, image processing method, and program
Method and system for placing an emergency call
Interconnect, bus system with interconnect and bus system operating method
Semiconductor unit having a power semiconductor and semiconductor apparatus using the same
System and method for improving cache efficiency
Brushless electric motor or generator in shell construction
  Randomly Featured Patents
7H-pyrrolo[2,3-d]pyrimidine derivatives
Structural panel incorporating clay grog and vermiculite and method for making said panel
Electric toothbrush
Methods for preventing and treating autoimmune and inflammatory disease using thioether furan nitrone compounds
Mass spectrometer with reduced static electric field
Crib
Pyrotechnic cap with mechanically desensitized composition
Handle for plumbing fittings
Apparatus for protecting mixer truck chute against wear
Oil-soluble chromium compositions