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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hattori; Yoshiyuki
Address:
Aichi-gun, JP
No. of patents:
10
Patents:




Patent Number Title Of Patent Date Issued
7553731 Method of manufacturing semiconductor device June 30, 2009
A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type
7465990 Semiconductor device having super junction structure December 16, 2008
A super junction type semiconductor device includes a first semiconductor layer of a first conductivity type, a super junction structure, and a second semiconductor layer of a second conductivity type. The thickness of the second semiconductor layer varies such that the thickness in the
7417284 Semiconductor device and method of manufacturing the same August 26, 2008
A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type
7364971 Method for manufacturing semiconductor device having super junction construction April 29, 2008
A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the fi
7345339 Vertical channel FET with super junction construction March 18, 2008
A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the fi
7342422 Semiconductor device having super junction structure and method for manufacturing the same March 11, 2008
A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semiconductor layer; a te
7342265 Vertical-type semiconductor device having repetitive-pattern layer March 11, 2008
A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure
7317213 Semiconductor device having super junction structure and method for manufacturing the same January 8, 2008
A semiconductor device includes: a center region; a periphery region; and a semiconductor layer including pairs of a first region having a first impurity amount and a second region having a second impurity amount. The first and the second regions are alternately aligned in a plane. The
7307312 Method of manufacturing a semiconductor device December 11, 2007
A semiconductor device manufacturing method comprises forming a pn column so that the pn column is designed to have a strip form in the section of the substrate and have a repetitive pattern of a p-conduction type and an n-conduction type on the substrate surface over an area where plura
7112519 Semiconductor device manufacturing method September 26, 2006
A semiconductor device includes: an n.sup.+ type drain region; an n type drift region that connects with the n.sup.+ type drain region; a p type body region; a n.sup.+ type source region that connects with the p type body region; and a gate electrode that is provided, with being covered


 
 
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