| Patent Number |
Title Of Patent |
Date Issued |
| 6798831 |
Testing system |
September 28, 2004 |
| A testing system is provided with a pseudo random number generating circuit which generates a pseudo random number on the basis of a 125 MHz clock output from a 5-multiply circuit inside a clock recovery circuit, and an expected value generating/comparator circuit which collates a 125 Mb |
| 6087869 |
Digital PLL circuit |
July 11, 2000 |
| A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that |
| 5859551 |
Digital PLL circuit |
January 12, 1999 |
| A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that |
| 5822557 |
Pipelined data processing device having improved hardware control over an arithmetic operations |
October 13, 1998 |
| An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein |
| 5778010 |
Method and device for correcting packet data error and packet receiver |
July 7, 1998 |
| A replacement control circuit 30, having a synchronization pattern monitoring circuit 31, an acquisition circuit 32, a tracking circuit 33, an RS flip-flop 34 and an AND gate 35, judges whether receive data D3 is in synchronization or not, counts a clock CLK corresponding to a byte of |
| 5742842 |
Data processing apparatus for executing a vector operation under control of a master processor |
April 21, 1998 |
| A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the |
| 5742839 |
Coprocessor for performing an arithmetic operation by automatically reading data from an externa |
April 21, 1998 |
| A processor comprises a command storage unit for storing a plurality of commands and data received from outside the processor, a command interpreter for interpreting commands and data stored in the command storage unit, an address designator for designating a particular execution add |
| 5508948 |
Numeric representation converting apparatus and vector processor unit such apparatus |
April 16, 1996 |
| A numeric representation converting apparatus comprises a weight determining circuit, a decimal alignment circuit, a converting circuit, and a selecting circuit. The weight determining circuit determines the weight of a mantissa part of an input floating-point number, based on the va |
