| Patent Number |
Title Of Patent |
Date Issued |
| 7624366 |
Clock aware placement |
November 24, 2009 |
| The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim c |
| 7487480 |
Method for estimating aggregate leakage of transistors |
February 3, 2009 |
| A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the co |
| 7444608 |
Method and system for evaluating timing in an integrated circuit |
October 28, 2008 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
| 7418689 |
Method of generating wiring routes with matching delay in the presence of process variation |
August 26, 2008 |
| A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a seco |
| 7404163 |
Static timing slacks analysis and modification |
July 22, 2008 |
| A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected |
| 7401307 |
Slack sensitivity to parameter variation based timing analysis |
July 15, 2008 |
| A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on eac |
| 7398491 |
Method for fast incremental calculation of an impact of coupled noise on timing |
July 8, 2008 |
| A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or mor |
| 7353477 |
Method of identifying paths with delays dominated by a particular factor |
April 1, 2008 |
| A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attri |
| 7325210 |
Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect |
January 29, 2008 |
| A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the |
| 7308669 |
Use of redundant routes to increase the yield and reliability of a VLSI layout |
December 11, 2007 |
| Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two element |
| 7280939 |
System and method of analyzing timing effects of spatial distribution in circuits |
October 9, 2007 |
| Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of i |
| 7225421 |
Clock tree distribution generation by determining allowed placement regions for clocked elements |
May 29, 2007 |
| A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by |
| 7142991 |
Voltage dependent parameter analysis |
November 28, 2006 |
| A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor |
| 7093208 |
Method for tuning a digital design for synthesized random logic circuit macros in a continuous d |
August 15, 2006 |
| A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommod |
| 7089143 |
Method and system for evaluating timing in an integrated circuit |
August 8, 2006 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
| 5535145 |
Delay model abstraction |
July 9, 1996 |
| An abstracted delay model for a circuit network is generated wherein each internal node and connecting edges of an inputted detailed delay graph are processed. All delay edges in the delay graph which could contribute to an extreme delay path from some primary input of the delay graph ar |
| 5282147 |
Method and apparatus for optimizing a logic network |
January 25, 1994 |
| A system for optimizing a logic network including expressing the logic network as an original graph having vertices, edges which connect the vertices and which represent connections in the logic network, and inversion markings for representing inverters in the logic network; determin |
