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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hatada; Akiyoshi
Address:
Kawasaki, JP
No. of patents:
23
Patents:












Patent Number Title Of Patent Date Issued
8278177 Semiconductor device and method of manufacturing the same October 2, 2012
A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first
8207042 Semiconductor device and method of manufacturing the same June 26, 2012
A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first
8164085 Semiconductor device and production method thereof April 24, 2012
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
8158498 P-channel MOS transistor and fabrication process thereof April 17, 2012
A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of
7968414 Semiconductor device and production method thereof June 28, 2011
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7883960 Method of manufacturing semiconductor device February 8, 2011
A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive la
7875521 Semiconductor device and production method thereof January 25, 2011
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7816766 Semiconductor device with compressive and tensile stresses October 19, 2010
A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate e
7791064 Semiconductor device and fabrication method thereof September 7, 2010
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation film
7683362 Semiconductor device and production method thereof March 23, 2010
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7667227 Semiconductor device and fabrication method thereof February 23, 2010
A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation film
7626215 Semiconductor device and method of manufacturing the same December 1, 2009
A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first
7579617 Semiconductor device and production method thereof August 25, 2009
A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type sem
7518188 P-channel MOS transistor and fabrication process thereof April 14, 2009
A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of
7476941 Semiconductor integrated circuit device and fabrication process thereof January 13, 2009
A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective
7378305 Semiconductor integrated circuit and fabrication process thereof May 27, 2008
A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate e
7262465 P-channel MOS transistor and fabrication process thereof August 28, 2007
A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si laye
7202120 Semiconductor integrated circuit device and fabrication process thereof April 10, 2007
A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective
6693002 Semiconductor device and its manufacture February 17, 2004
A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing
6586794 Semiconductor device and its manufacture July 1, 2003
A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing
6159858 Slurry containing manganese oxide and a fabrication process of a semiconductor device using such December 12, 2000
A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
5877089 Slurry containing manganese oxide March 2, 1999
A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
5763325 Fabrication process of a semiconductor device using a slurry containing manganese oxide June 9, 1998
A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.










 
 
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