| Patent Number |
Title Of Patent |
Date Issued |
| 7381607 |
Method of forming a spiral inductor in a semiconductor substrate |
June 3, 2008 |
| An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar |
| 7259927 |
Method and apparatus for improving signal-to-noise ratio for hard disk drives |
August 21, 2007 |
| A hard disk drive comprising a plurality of read/write heads oriented to serially read data from the magnetic media of the disk drive. The head output signals are delayed and combined to provide a time aligned composite signal for determining the value of the data bits read from the |
| 7075167 |
Spiral inductor formed in a semiconductor substrate |
July 11, 2006 |
| An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar |
| 6741147 |
Method and apparatus for adjusting the resonant frequency of a thin film resonator |
May 25, 2004 |
| A thin film resonator comprising a piezoelectric material and having a controllable or tunable resonant frequency. The resonator is formed on a substrate having a cavity formed therein below the piezoelectric film material. A bending electrode is disposed within the cavity and the ap |
| 6576563 |
Method of manufacturing a semiconductor device employing a fluorine-based etch substantially fre |
June 10, 2003 |
| The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said materi |
| 6570238 |
Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation |
May 27, 2003 |
| A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second |
| 6323111 |
Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation |
November 27, 2001 |
| A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second |
