| Patent Number |
Title Of Patent |
Date Issued |
| 7437635 |
Testing hard-wired IP interface signals using a soft scan chain |
October 14, 2008 |
| A set of boundary scan registers are implemented by reconfiguring the functional blocks of a reconfigurable device. This "soft-wired" set of boundary scan registers can be used to test the interface connections between the IP core and the functional blocks of the reconfigurable devic |
| 7319341 |
Method of maintaining signal integrity across a capacitive coupled solder bump |
January 15, 2008 |
| The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms |
| 7111213 |
Failure isolation and repair techniques for integrated circuits |
September 19, 2006 |
| Techniques for isolating and repairing failures on a programmable circuit are provided. An error on programmable circuit may be caused by a defect on the chip. The error is located, and the circuit elements effected by the defect are isolated. By identifying operable circuit elements nea |
| 7062685 |
Techniques for providing early failure warning of a programmable circuit |
June 13, 2006 |
| Techniques for monitoring the performance of a programmable circuit and to provide an early warning of a potential failure are provided. A processor monitors the performance of components on a programmable circuit over time. The processor stores performance characteristics for the compon |
| 7058534 |
Method and apparatus for application specific test of PLDs |
June 6, 2006 |
| Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application |
| 7024327 |
Techniques for automatically generating tests for programmable circuits |
April 4, 2006 |
| Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmab |
