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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Harberts; Dirk W.
Address:
Eindhoven, NL
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
6242856 Cathode ray tube comprising a deflection unit June 5, 2001
A cathode ray tube includes a deflection unit. A coil system of the deflection unit is provided with a conductive layer, the value for f.sub.max /.DELTA.f ranging between 0.5 and 10, .DELTA.f being the half-value width of the impedance curve around a peak frequency f.sub.max, and f.s
5986399 Display device November 16, 1999
In, for example a field emission display, the invention provides the possibility of combining a plurality of sub-substrates that are attached to a larger rear wall, because notably different modes of multiplexing provide a wider positioning tolerance of a sub-substrate with respect to
5801485 Display device September 1, 1998
In, for example a field emission display, the invention provides the possibility of combining a plurality of sub-substrates that are attached to a larger rear wall, because notably different modes of multiplexing provide a wider positioning tolerance of a sub-substrate with respect to
5537007 Field emitter display device with two-pole circuits July 16, 1996
By incorporating two-pole circuits (13) as switching elements in a picture display device based on field emission, the emission (and hence the picture intensity) is substantially defined by the charge of a capacitance (15) associated with a part of a pixel (8). Charge-controlled drive le
5250823 Integrated CMOS gate-array circuit October 5, 1993
A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at l
5053648 Master slice CMOS array having complementary columns October 1, 1991
A master slice semiconductor integrated circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same ro










 
 
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