| Patent Number |
Title Of Patent |
Date Issued |
| 7555050 |
Space-time block coding system combined with local polynomial approximation based beamformer |
June 30, 2009 |
| Provided is an STBC transceiving system with LPA-based beamformer, including: an STBC encoder having branches, in number of D, to generate output signals in number of D for an input signal; a beamformer having output antennas in number of D*B, being comprised of beam-forming subarray |
| 7519643 |
Montgomery multiplier for RSA security module |
April 14, 2009 |
| A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines me |
| 7512190 |
Data transmission apparatus using asynchronous dual-rail bus and method therefor |
March 31, 2009 |
| The present invention relates to a data transmission apparatus using an asynchronous dual-rail bus and a method therefor which can reduce power consumption for transferring data by limiting the number of dual-rail buses transferring data when a transmission side transfers an identical |
| 7467358 |
Asynchronous switch based on butterfly fat-tree for network on chip application |
December 16, 2008 |
| The present invention disclosed herein is an asynchronous switch for an network on chip application making possible between IP (Intellectual Property) communication among various IPs in the network on chip. The asynchronous switch according to the present invention in which comprises |
| 7313672 |
Intellectual property module for system-on-chip |
December 25, 2007 |
| Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control signal which leads |
| 7282946 |
Delay-insensitive data transfer circuit using current-mode multiple-valued logic |
October 16, 2007 |
| The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire.The delay-insensitive data transfer circuit of the present invent |
| 7170431 |
Data transmitting circuit and method based on differential value data encoding |
January 30, 2007 |
| Disclosed is a data transmitting circuit and a method based on a differential value data encoding to reduce a data transmitting time by transmitting an encoded differential value. The circuit comprises an encoder for encoding and outputting a differential value between a currently tr |
