| Patent Number |
Title Of Patent |
Date Issued |
| 7598547 |
Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to |
October 6, 2009 |
| We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer con |
| 7307309 |
EEPROM with etched tunneling window |
December 11, 2007 |
| A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity |
| 7268394 |
JFET structure for integrated circuit and fabrication method |
September 11, 2007 |
| Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold |
| 7244651 |
Fabrication of an OTP-EPROM having reduced leakage current |
July 17, 2007 |
| The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the V.sub.tp implant into a channel region of an n-well that substantially underlies a fl |
| 7235451 |
Drain extended MOS devices with self-aligned floating region and fabrication methods therefor |
June 26, 2007 |
| Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an |
| 7208364 |
Methods of fabricating high voltage devices |
April 24, 2007 |
| Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer |
| 7164160 |
Integrated circuit device with a vertical JFET |
January 16, 2007 |
| We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer con |
| 7135373 |
Reduction of channel hot carrier effects in transistor devices |
November 14, 2006 |
| A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. |
| 7122862 |
Reduction of channel hot carrier effects in transistor devices |
October 17, 2006 |
| A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. |
| 7045418 |
Semiconductor device including a dielectric layer having a gettering material located therein an |
May 16, 2006 |
| The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wher |
| 7018880 |
Method for manufacturing a MOS transistor having reduced 1/f noise |
March 28, 2006 |
| The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The metho |
| 7005354 |
Depletion drain-extended MOS transistors and methods for making the same |
February 28, 2006 |
| Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate |
| 6885054 |
Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same |
April 26, 2005 |
| The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes a body well located in a substrate, a source located in the body well, and a stabilization |
| 6861303 |
JFET structure for integrated circuit and fabrication method |
March 1, 2005 |
| Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold |
| 6794700 |
Capacitor having a dielectric layer including a group 17 element |
September 21, 2004 |
| The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conduct |
