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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Han; Jin-Ping
Address:
Fishkill, NY
No. of patents:
22
Patents:












Patent Number Title Of Patent Date Issued
8252649 Methods of fabricating semiconductor devices and structures thereof August 28, 2012
Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at
8198194 Methods of forming p-channel field effect transistors having SiGe source/drain regions June 12, 2012
Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spac
8138055 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain region March 20, 2012
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate
8106462 Balancing NFET and PFET performance using straining layers January 31, 2012
An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on th
8063449 Semiconductor devices and methods of manufacture thereof November 22, 2011
Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least
8017472 CMOS devices having stress-altering material lining the isolation trenches and methods of manufa September 13, 2011
Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-alter
7955936 Semiconductor fabrication process including an SiGe rework method June 7, 2011
A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and exc
7951664 Methods of manufacturing resistors and structures thereof May 31, 2011
Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack,
7947606 Methods of forming conductive features and structures thereof May 24, 2011
Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a lower portion of the feature in the first material, and filling the first pattern with a
7935593 Stress optimization in dual embedded epitaxially grown semiconductor processing May 3, 2011
Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo implantation masks for
7893502 Threshold voltage improvement employing fluorine implantation and adjustment oxide layer February 22, 2011
An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transist
7892939 Threshold voltage consistency and effective width in same-substrate device groups February 22, 2011
The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure t
7842592 Channel strain engineering in field-effect-transistor November 30, 2010
There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stre
7838372 Methods of manufacturing semiconductor devices and structures thereof November 23, 2010
Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the
7820518 Transistor fabrication methods and structures thereof October 26, 2010
Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing mater
7800182 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain region September 21, 2010
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stac
7795107 Method for forming isolation structures September 14, 2010
A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.
7772676 Strained semiconductor device and method of making same August 10, 2010
A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor m
7737468 Semiconductor devices having recesses filled with semiconductor materials June 15, 2010
Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semico
7696019 Semiconductor devices and methods of manufacturing thereof April 13, 2010
Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first re
7652336 Semiconductor devices and methods of manufacture thereof January 26, 2010
Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one
7615840 Device performance improvement using flowfill as material for isolation structures November 10, 2009
A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.










 
 
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