| Patent Number |
Title Of Patent |
Date Issued |
| 8179721 |
Non-volatile memory device with both single and multiple level cells |
May 15, 2012 |
| A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word |
| 8174889 |
Programming memory devices |
May 8, 2012 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 8072816 |
Memory block reallocation in a flash memory device |
December 6, 2011 |
| A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline |
| 8064258 |
Method apparatus, and system providing adjustable memory page configuration |
November 22, 2011 |
| A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use. |
| 7855927 |
NAND system with a data write frequency greater than a command-and-address-load frequency |
December 21, 2010 |
| The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency. |
| 7808822 |
Non-volatile memory device with both single and multiple level cells |
October 5, 2010 |
| A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word |
| 7707368 |
Memory device trims |
April 27, 2010 |
| Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to |
| 7688630 |
Programming memory devices |
March 30, 2010 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7630236 |
Flash memory programming to reduce program disturb |
December 8, 2009 |
| The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than V.sub.pass. The memory cells on this unsel |
| 7558131 |
NAND system with a data write frequency greater than a command-and-address-load frequency |
July 7, 2009 |
| The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency. |
| 7551510 |
Memory block reallocation in a flash memory device |
June 23, 2009 |
| A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline |
| 7548459 |
Method, apparatus, and system providing adjustable memory page configuration |
June 16, 2009 |
| A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use. |
| 7542336 |
Architecture and method for NAND flash memory |
June 2, 2009 |
| A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at |
| 7518914 |
Non-volatile memory device with both single and multiple level cells |
April 14, 2009 |
| A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word |
| 7505323 |
Programming memory devices |
March 17, 2009 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7447847 |
Memory device trims |
November 4, 2008 |
| Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to |
| 7400549 |
Memory block reallocation in a flash memory device |
July 15, 2008 |
| A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline |
| 7372715 |
Architecture and method for NAND flash memory |
May 13, 2008 |
| A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at |
| 7369447 |
Random cache read |
May 6, 2008 |
| A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is us |
| 7345924 |
Programming memory devices |
March 18, 2008 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7269066 |
Programming memory devices |
September 11, 2007 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7196930 |
Flash memory programming to reduce program disturb |
March 27, 2007 |
| The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than V.sub.pass. The memory cells on this unsel |
| 7123521 |
Random cache read |
October 17, 2006 |
| A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is us |
| 6845037 |
Reference cells for TCCT based memory cells |
January 18, 2005 |
| A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an "on" state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR d |
| 6778435 |
Memory architecture for TCCT-based memory cells |
August 17, 2004 |
| A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical "0" and |
| 6611452 |
Reference cells for TCCT based memory cells |
August 26, 2003 |
| A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an "on" state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR d |
