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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Han; Byung Joon
Address:
Singapore, SG
No. of patents:
35
Patents:












Patent Number Title Of Patent Date Issued
8269356 Wire bonding structure and method that eliminates special wire bondable finish and reduces bondi September 18, 2012
A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The
8198735 Integrated circuit package with molded cavity June 12, 2012
An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integr
8163600 Bridge stack integrated circuit package-on-package system April 24, 2012
A bridge stack integrated circuit package-on-package system is provided including forming a first integrated circuit package system having a first substrate, forming a second integrated circuit package system having a second substrate, and mounting a bridge integrated circuit package
8125073 Wafer integrated with permanent carrier and method therefor February 28, 2012
A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect s
8050047 Integrated circuit package system with flexible substrate and recessed package November 1, 2011
An integrated circuit package system includes: providing a flexible circuit substrate having a fold; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulati
8031475 Integrated circuit package system with flexible substrate and mounded package October 4, 2011
An integrated circuit package system includes: providing a flexible circuit substrate; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integra
8021924 Encapsulant cavity integrated circuit package system and method of fabrication thereof September 20, 2011
A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
7969023 Integrated circuit package system with triple film spacer having embedded fillers and method of June 28, 2011
An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first
7880293 Wafer integrated with permanent carrier and method therefor February 1, 2011
A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect s
7868468 Wire bonding structure and method that eliminates special wire bondable finish and reduces bondi January 11, 2011
A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The seco
7855100 Integrated circuit package system with an encapsulant cavity and method of fabrication thereof December 21, 2010
An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
7790504 Integrated circuit package system September 7, 2010
An integrated circuit package system is provided providing a first structure, forming a compression via in the first structure, forming a stud bump on a second structure and pressing the stud bump into the compression via forming a mechanical bond.
7746656 Offset integrated circuit package-on-package stacking system June 29, 2010
An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, providing an array of contact pads on the base substrate, mounting an active component and an optional passive component on the base substrate, injecting a mold cap on th
7733661 Chip carrier and fabrication method June 8, 2010
A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the
7732907 Integrated circuit package system with edge connection system June 8, 2010
An integrated circuit package system including a plurality of substrates and a plurality of semiconductor devices formed on each of the substrates. An edge connection system is provided and an electrical edge connector on each of the substrates is for attachment to the edge connectio
7518224 Offset integrated circuit package-on-package stacking system April 14, 2009
An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, forming a contact pad on the base substrate, mounting a first integrated circuit on the base substrate, forming a base package body around the first integrated circuit, p
7435619 Method of fabricating a 3-D package stacking system October 14, 2008
The present invention provides a system for 3D package stacking system, comprising providing a substrate, attaching a ball grid array package, in an inverted position, to the substrate, forming a lower package, the lower package having the ball grid array package and the substrate en
7429787 Semiconductor assembly including chip scale package and second substrate with exposed surfaces o September 30, 2008
Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second ("land") side, mounted over the molding of the first
7413933 Integrated circuit package with leadframe locked encapsulation and method of manufacture therefo August 19, 2008
A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connect
7372141 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower side May 13, 2008
Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other, that is, the die attach sides of the package
7364945 Method of mounting an integrated circuit package in an encapsulant cavity April 29, 2008
An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
7309913 Stacked semiconductor packages December 18, 2007
A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is
7304859 Chip carrier and fabrication method December 4, 2007
A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the
7217599 Integrated circuit package with leadframe locked encapsulation and method of manufacture therefo May 15, 2007
A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connect
7135760 Moisture resistant integrated circuit leadframe package November 14, 2006
A leadframe for a semiconductor die includes signal leads, ground leads, and a die support holder for supporting the semiconductor die. The die support holder has opposite surfaces and side edges therebetween. The opposite die support holder surfaces are smaller in transverse extent
7091596 Semiconductor packages and leadframe assemblies August 15, 2006
Semiconductor packages provide a leadframe for packages that are singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps
7064420 Integrated circuit leadframe with ground plane June 20, 2006
A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incor
6876069 Ground plane for exposed package April 5, 2005
A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
6861288 Stacked semiconductor packages and method for the fabrication thereof March 1, 2005
A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the subs
6858470 Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication ther February 22, 2005
A method for fabricating semiconductor packages provides a leadframe for packages that are to be singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined packag
6803254 Wire bonding method for a semiconductor package October 12, 2004
A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patter
6642610 Wire bonding method and semiconductor package manufactured using the same November 4, 2003
A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of th
6630373 Ground plane for exposed package October 7, 2003
A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.
6489667 Semiconductor device and method of manufacturing such device December 3, 2002
Semiconductor devices and methods of manufacturing such devices are disclosed. In one embodiment of this invention, a semiconductor chip is bonded to a first surface of a substrate. The substrate extends beyond the edge of the chip. Signal input/output pads on the chip are juxtaposed wit
6414396 Package for stacked integrated circuits July 2, 2002
Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One integrated circuit package comprises a substrate having a first surface having first metallizations thereon, an opposite second surf










 
 
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