| Patent Number |
Title Of Patent |
Date Issued |
| 6430670 |
Apparatus and method for a virtual hashed page table |
August 6, 2002 |
| The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of |
| 6430657 |
COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUC |
August 6, 2002 |
| Atomic memory operations are provided by using exportable "fetch and add" instructions and by emulating IA-32 instructions prepended with a lock prefix. In accordance with the present invention, a CPU includes a default control register that includes IA-32 lock check enable bit (LC) that |
| 6408373 |
Method and apparatus for pre-validating regions in a virtual addressing scheme |
June 18, 2002 |
| A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can |
| 6216214 |
Apparatus and method for a virtual hashed page table |
April 10, 2001 |
| The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of |
| 6209085 |
Method and apparatus for performing process switching in multiprocessor computer systems |
March 27, 2001 |
| A method and apparatus for reducing the amount of data copied during process switches. A method for reducing the amount of data copied during process switches is provided. In response to a processor performing a process switch to a process, a first write indication corresponding to the |
| 6199144 |
Method and apparatus for transferring data in a computer system |
March 6, 2001 |
| A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. |
| 6148321 |
Processor event recognition |
November 14, 2000 |
| A method and apparatus for the incorporation of additional processor generated events. The processor generally comprises a storage area, an indication unit, and a retriever. The storage area stores an indication. Upon recognition of each event, the indication unit alters the state of |
| 6128706 |
Apparatus and method for a load bias--load with intent to semaphore |
October 3, 2000 |
| Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints t |
| 6088780 |
Page table walker that uses at least one of a default page size and a page size selected for a v |
July 11, 2000 |
| A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer sy |
| 6065115 |
Processor and method for speculatively executing instructions from multiple instruction streams |
May 16, 2000 |
| A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved t |
| 6055652 |
Multiple segment register use with different operand size |
April 25, 2000 |
| A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possibl |
| 6052801 |
Method and apparatus for providing breakpoints on a selectable address range |
April 18, 2000 |
| A method and apparatus for providing breakpoints on a selectable address range. The apparatus generally includes a processor including a first storage area, a second storage area, a circuit and an execution unit. The first storage area has stored therein a first address, while the second |
| 6049897 |
Multiple segment register use with different operand size |
April 11, 2000 |
| A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possibl |
| 6012132 |
Method and apparatus for implementing a page table walker that uses a sliding field in the virtu |
January 4, 2000 |
| A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a |
| 6006325 |
Method and apparatus for instruction and data serialization in a computer processor |
December 21, 1999 |
| A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a |
| 5940872 |
Software and hardware-managed translation lookaside buffer |
August 17, 1999 |
| A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a se |
| 5918251 |
Method and apparatus for preloading different default address translation attributes |
June 29, 1999 |
| A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute |
| 5918250 |
Method and apparatus for preloading default address translation attributes |
June 29, 1999 |
| A method and apparatus for installing translations in a translation look-aside buffer. According to the method, each translation contains either a first attribute or a second attribute. Either the first attribute or the second attribute is selected as a default attribute to be preloaded |
| 5915117 |
Computer architecture for the deferral of exceptions on speculative instructions |
June 22, 1999 |
| The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardw |
| 5895489 |
Memory management system including an inclusion bit for maintaining cache coherency |
April 20, 1999 |
| A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a des |
| 5860017 |
Processor and method for speculatively executing instructions from multiple instruction streams |
January 12, 1999 |
| A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved t |
| 5832260 |
Processor microarchitecture for efficient processing of instructions in a program including a co |
November 3, 1998 |
| A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the pro |
| 5752275 |
Translation look-aside buffer including a single page size translation unit |
May 12, 1998 |
| A method and apparatus for use in a computer system to translate virtual addresses into translated addresses. According to one aspect of the invention, a dynamically configurable translation unit is provided. Based on a value stored in a storage area, the dynamically configurable tra |
| 5659679 |
Method and apparatus for providing breakpoints on taken jumps and for providing software profili |
August 19, 1997 |
| According to one aspect of the invention, an apparatus for providing the source address of an instruction which causes a branch to be taken (e.g., instructs the processor to transfer the flow of execution) is described. In one embodiment, a processor includes a circuit coupled to a sourc |
| 5638525 |
Processor capable of executing programs that contain RISC and CISC instructions |
June 10, 1997 |
| A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer pro |
| 5283874 |
Cross coupling mechanisms for simultaneously completing consecutive pipeline instructions even i |
February 1, 1994 |
| Apparatus and methods for expediting the completion of microprocessor instructions using a microprocessor pipelining system. Two or more dependent instructions processed through two or more microprocessor pipelines are simultaneously completed. This simultaneous completion of the two |
