| Patent Number |
Title Of Patent |
Date Issued |
| 5359216 |
DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
October 25, 1994 |
| The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacit |
| 5302539 |
VLSI interconnect method and structure |
April 12, 1994 |
| A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. Howev |
| 5244825 |
DRAM process with improved poly-to-poly capacitor |
September 14, 1993 |
| The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacit |
| 5141890 |
CMOS sidewall oxide-lightly doped drain process |
August 25, 1992 |
| A CMOS process wherein lightly doped drain extensions are fabricated in the N-channel devices without any additional masking steps. The present invention requires a specific sequence of steps, after all steps through patterning of the polysilicon gate level have been completed: first, a |
| 5098192 |
DRAM with improved poly-to-poly capacitor |
March 24, 1992 |
| The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) |
| 5021851 |
NMOS source/drain doping with both P and As |
June 4, 1991 |
| A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing |
| 5010032 |
Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and |
April 23, 1991 |
| A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing |
| 4975756 |
SRAM with local interconnect |
December 4, 1990 |
| An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density. |
| 4949154 |
Thin dielectrics over polysilicon |
August 14, 1990 |
| The present invention teaches a new method for formation of thin dielectrics over polysilicon. This technique permits the fabrication of poly-to-poly capacitors with high specific capacitance (capacitance per unit area). This technique is completely compatible with standard MOS dual |
| 4922312 |
DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
May 1, 1990 |
| The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) |
| 4890141 |
CMOS device with both p+ and n+ gates |
December 26, 1989 |
| A CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. |
| 4851360 |
NMOS source/drain doping with both P and As |
July 25, 1989 |
| A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealling, the source/drain regions have graded regions of gradually decreasin |
| 4821085 |
VLSI local interconnect structure |
April 11, 1989 |
| A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. Normally this conductive layer is stripped to avoid shorting out devices. Howev |
| 4804636 |
Process for making integrated circuits having titanium nitride triple interconnect |
February 14, 1989 |
| Disclosed is a process for making VLSI integrated circuits and a local interconnect system, wherein first poly, second poly and moat are all interconnected in any desired pattern by a TiN local interconnect. No masks are required beyond those which would be required for the two poly |
| 4746219 |
Local interconnect |
May 24, 1988 |
| A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overa |
| 4690730 |
Oxide-capped titanium silicide formation |
September 1, 1987 |
| A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide. |
| 4676866 |
Process to increase tin thickness |
June 30, 1987 |
| A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken |
| 4657628 |
Process for patterning local interconnects |
April 14, 1987 |
| A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overa |
| 4656732 |
Integrated circuit fabrication process |
April 14, 1987 |
| Integrated circuits wherein the width of contacts is narrowed by a sidewall oxide, so that the metal layer can be patterned to minimum geometry everywhere, and does not have to be widened where it runs over a contact. |
| 4613956 |
Floating gate memory with improved dielectric |
September 23, 1986 |
| The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide |
| 4613885 |
High-voltage CMOS process |
September 23, 1986 |
| A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for th |
| 4590663 |
High voltage CMOS technology with N-channel source/drain extensions |
May 27, 1986 |
| N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of the N-channel gates, expanded by two alignment tolerances per side, combined with the regula |
| 4587718 |
Process for forming TiSi.sub.2 layers of differing thicknesses in a single integrated circuit |
May 13, 1986 |
| Using a process in accordance with the teachings of this invention, an integrated circuit may be fabricated providing refractory metal silicide layers, such as TiSi.sub.2, of differing thicknesses to provide optimal reductions in the sheet resistances of the regions in which refractory |
| 4577390 |
Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer |
March 25, 1986 |
| The present invention teaches a new method for formation of thin dielectrics over polysilicon. This technique permits the fabrication of polysilicon to polysilicon capacitors with high specific capacitance (per unit area). This technique is completely compatible with standard MOS dual |
| 4524431 |
High-speed nonvolatile memory array |
June 18, 1985 |
| A memory array using nonvolatile memory elements. Preferably multi-dielectric transistors are used to provide nonvolatile information storage. Good write speed is attained by providing a relatively low barrier to carrier injection. To compensate for the resulting low storage time, pe |
| 4521446 |
Method for depositing polysilicon over TiO.sub.2 |
June 4, 1985 |
| Hydrogen annealing permits deposition of good quality polysilicon atop TiO.sub.2. Hydrogen annealing of TiO.sub.2 prevents the tremendous hydrogen affinity of as-deposited TiO.sub.2 from disrupting process reactions during deposition of polysilicon. |
| 4472791 |
CMOS Unipolar nonvolatile memory cell |
September 18, 1984 |
| A CMOS nonvolatile memory cell, where a multiple-dielectric P-channel device is used to provide nonvolatile information storage. An N-channel device is used to limit current (and thus power dissipation) during write operations, and two other transistors are both controlled by a single wo |
| 4442591 |
High-voltage CMOS process |
April 17, 1984 |
| A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for th |
