| Patent Number |
Title Of Patent |
Date Issued |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
June 30, 2009 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 7487333 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
February 3, 2009 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7162610 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 9, 2007 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7028161 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
April 11, 2006 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6986024 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 10, 2006 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor |
November 15, 2005 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 25, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6954844 |
Microprocessor architecture capable of supporting multiple heterogeneous processors |
October 11, 2005 |
| A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of t |
| 6948052 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 20, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6941447 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 6, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6934829 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 23, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6915412 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 5, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6647485 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
November 11, 2003 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6611908 |
Microprocessor architecture capable of supporting multiple heterogeneous processors |
August 26, 2003 |
| A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of t |
| 6282630 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
August 28, 2001 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6272619 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 7, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6272579 |
Microprocessor architecture capable of supporting multiple heterogeneous processors |
August 7, 2001 |
| A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic |
| 6256720 |
High performance, superscalar-based computer system with out-of-order instruction execution |
July 3, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6219763 |
System and method for adjusting priorities associated with multiple devices seeking access to a |
April 17, 2001 |
| A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include |
| 6173369 |
Computer system for processing multiple requests and out of order returns using a request queue |
January 9, 2001 |
| A system and method for processing a sequence of requests for data by one or more central processing units (CPUs) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU issuing the request for data and an address identifying a location in lower-level memory where |
| 6128723 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 3, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6101594 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 8, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6092181 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 18, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038654 |
High performance, superscalar-based computer system with out-of-order instruction execution |
March 14, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038653 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
March 14, 2000 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5961629 |
High performance, superscalar-based computer system with out-of-order instruction execution |
October 5, 1999 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 5941979 |
Microprocessor architecture with a switch network and an arbitration unit for controlling access |
August 24, 1999 |
| A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O |
| 5832292 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
November 3, 1998 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5778434 |
System and method for processing multiple requests and out of order returns |
July 7, 1998 |
| A system and method for processing a sequence of requests for data by one or more central processing units (CPUs) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU issuing the request for data and an address identifying a location in lower-level memory where |
| 5754800 |
Multi processor system having dynamic priority based on row match of previously serviced address |
May 19, 1998 |
| A computer system comprising a multiprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O |
| 5689720 |
High-performance superscalar-based computer system with out-of-order instruction execution |
November 18, 1997 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instr |
| 5604865 |
Microprocessor architecture with a switch network for data transfer between cache, memory port, |
February 18, 1997 |
| A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory are handled using a switch network. Access to memory buses is controlled by arbitration circuits which u |
| 5560032 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
September 24, 1996 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program ins |
| 5539911 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 23, 1996 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instr |
| 5481685 |
RISC microprocessor architecture implementing fast trap and exception state |
January 2, 1996 |
| Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler c |
| 5448705 |
RISC microprocessor architecture implementing fast trap and exception state |
September 5, 1995 |
| A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main |
| 5440752 |
Microprocessor architecture with a switch network for data transfer between cache, memory port, |
August 8, 1995 |
| A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which ut |
