| Patent Number |
Title Of Patent |
Date Issued |
| 7620921 |
IC chip at-functional-speed testing with process coverage evaluation |
November 17, 2009 |
| Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust |
| 7555740 |
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corne |
June 30, 2009 |
| Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated ci |
| 7489204 |
Method and structure for chip-level testing of wire delay independent of silicon delay |
February 10, 2009 |
| Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to ei |
| 7464359 |
Method for re-routing an interconnection array to improve switching behavior in a single net and |
December 9, 2008 |
| Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as |
| 7444608 |
Method and system for evaluating timing in an integrated circuit |
October 28, 2008 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
| 7418689 |
Method of generating wiring routes with matching delay in the presence of process variation |
August 26, 2008 |
| A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a seco |
| 7401307 |
Slack sensitivity to parameter variation based timing analysis |
July 15, 2008 |
| A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on eac |
| 7289659 |
Method and apparatus for manufacturing diamond shaped chips |
October 30, 2007 |
| In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that ar |
| 7266474 |
Ring oscillator structure and method of separating random and systematic tolerance values |
September 4, 2007 |
| A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic dela |
| 7181711 |
Prioritizing of nets for coupled noise analysis |
February 20, 2007 |
| A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack |
| 7089143 |
Method and system for evaluating timing in an integrated circuit |
August 8, 2006 |
| Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An |
| 7089129 |
Electromigration check of signal nets using net capacitance to evaluate thermal characteristics |
August 8, 2006 |
| A method for performing an electromigration check and detecting EM problems in a device or circuit. The method uses the capacitance and resistance of the conductors of the device or circuit as parameters in determining a power limit that maintains a required temperature environment t |
| 6948146 |
Simplified tiling pattern method |
September 20, 2005 |
| The invention provides a design and an integrated circuit having a substantially uniform density and electrical characteristics between parts of the IC that are angled at 45 degrees relative to one another. In particular, the invention provides fill tiling patterns oriented substanti |
| 6854099 |
Balanced accuracy for extraction |
February 8, 2005 |
| A method and system for performing parasitic extraction, wherein the method comprises calculating the minimum output impedance for a network-connected component comprising a plurality of ports thereby producing a labeled impedance, estimating the minimum output impedance for every net, |
| 6848089 |
Method and apparatus for detecting devices that can latchup |
January 25, 2005 |
| A method and apparratus for for identifying circuits within an integrated circuit design that are likely to latchup. The present invention accomplishes the identification by searching for suspect circuits and then modifying these circuits to represent a device known by an EDA tool (e.g. |
| 6757876 |
Method for use of hierarchy in extraction |
June 29, 2004 |
| A method and system for extracting circuit characteristics from a circuit design comprises extracting first cell characteristics from a portion of said circuit design using a first set of environmental conditions. The invention then extracts second cell characteristics from the portion o |
| 6624651 |
Kerf circuit for modeling of BEOL capacitances |
September 23, 2003 |
| A kerf circuit for modeling of Back End Of Line (BEOL) capacitances is disclosed. The kerf circuit contains a clock circuit connected to a number of capacitance testing circuits. Each capacitance testing circuit acts a "bay" that can be configured to test one particular capacitance. The |
| 6574782 |
Decoupled capacitance calculator for orthogonal wiring patterns |
June 3, 2003 |
| A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segm |
| 6519752 |
Method of performing parasitic extraction for a multi-fingered transistor |
February 11, 2003 |
| A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the finge |
| 6490708 |
Method of integrated circuit design by selection of noise tolerant gates |
December 3, 2002 |
| A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and order |
| 6477686 |
Method of calculating 3-dimensional fringe characteristics using specially formed extension shap |
November 5, 2002 |
| A structure and method for performing a capacitance extraction on an integrated circuit, includes determining a parallel-plate capacitance between devices on different levels within the integrated circuit, adding extension shapes around each of the devices, reducing an area of overla |
| 6473887 |
Inclusion of global wires in capacitance extraction |
October 29, 2002 |
| A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency |
| 6460167 |
Efficient system for multi-level shape interactions |
October 1, 2002 |
| A structure and method for evaluating an integrated circuit design includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the |
| 6430729 |
Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-th |
August 6, 2002 |
| A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices ba |
| 5761080 |
Method and apparatus for modeling capacitance in an integrated circuit |
June 2, 1998 |
| According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjuste |
