Resources Contact Us Home Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE     Inventor: Gupta; Rajesh Address: Poughkeepsie, NY No. of patents: 1 Patents: Patent Number Title Of Patent Date Issued 5731985 Chip sizing for hierarchical designs March 24, 1998 A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning proc       Recently Added Patents Integration of COTS software data stores into integrated data access layer Liquid ejection head Dual piston, single phase sampling mechanism and procedure Method of encapsulating an organic light-emitting device Compton scattered X-ray visualization, imaging, or information provider with scattering event locating Upper for a shoe Glucocortioid mimetics, methods of making them, pharmaceutical compositions, and uses thereof   Randomly Featured Patents DC compound motor having an auxiliary generator which supplies power for shunt field winding excitation Water closet Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Network based muting of a cellular telephone Pumping feature on wear sleeve for unitized seal Semiconductor device Foils Solvent-free mechanochemical preparation of phosphonium salts, phosphorus ylides, and olefins Substrate with locally integrated single crystalline silicon layer and method of fabricating the same ECL terminator comprised of a plural resistor network © 2006. PatentGenius. All Rights Reserved.