| Patent Number |
Title Of Patent |
Date Issued |
| 7553772 |
Process and apparatus for simultaneous light and radical surface treatment of integrated circuit |
June 30, 2009 |
| Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with |
| 7341978 |
Superconductor wires for back end interconnects |
March 11, 2008 |
| An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the elect |
| 7259462 |
Interconnect dielectric tuning |
August 21, 2007 |
| An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the |
| 7081406 |
Interconnect dielectric tuning |
July 25, 2006 |
| An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the |
| 6972840 |
Method of reducing process plasma damage using optical spectroscopy |
December 6, 2005 |
| Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging vol |
| 6893937 |
Method for preventing borderless contact to well leakage |
May 17, 2005 |
| An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxi |
| 6875702 |
Plasma treatment system |
April 5, 2005 |
| A process for forming a conductive via in an integrated circuit structure that includes a first dielectric layer overlying a first conductive layer. A via cavity is formed in the first dielectric layer, which exposes the first conductive layer. A titanium nitride liner layer is formed in |
| 6818516 |
Selective high k dielectrics removal |
November 16, 2004 |
| A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, ther |
| 6806038 |
Plasma passivation |
October 19, 2004 |
| A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrai |
| 6794304 |
Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene |
September 21, 2004 |
| A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially |
| 6746925 |
High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation |
June 8, 2004 |
| In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O.sub.2 plasma oxidation. The p |
| 6743669 |
Method of reducing leakage using Si3N4 or SiON block dielectric films |
June 1, 2004 |
| A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si.sub.3 N.sub.4 is disposed on the oxide |
| 6673200 |
Method of reducing process plasma damage using optical spectroscopy |
January 6, 2004 |
| Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging vol |
| 6551901 |
Method for preventing borderless contact to well leakage |
April 22, 2003 |
| An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxi |
| 6498045 |
Optical intensity modifier |
December 24, 2002 |
| A method for detecting an end point of an etching step conducted in an etching chamber. A target emission intensity level is selected for the etching step, and the etching step is performed in the etching chamber. A raw emission intensity level is sensed from the etching chamber during t |
