| Patent Number |
Title Of Patent |
Date Issued |
| 8255884 |
Optimized scalar promotion with load and splat SIMD instructions |
August 28, 2012 |
| Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original |
| 8188761 |
Soft error detection for latches |
May 29, 2012 |
| A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and |
| 8166279 |
Method for predictive decoding of a load tagged pointer instruction |
April 24, 2012 |
| Predictive decoding is achieved by fetching an instruction, accessing a predictor containing predictor information including prior instruction execution characteristics, obtaining predictor information for the fetched instruction from the predictor; and generating a selected one of a |
| 8127078 |
High performance unaligned cache access |
February 28, 2012 |
| A cache memory device and method for operating the same. One embodiment of the cache memory device includes an address decoder decoding a memory address and selecting a target cache line. A first cache array is configured to output a first cache entry associated with the target cache |
| 8108846 |
Compiling scalar code for a single instruction multiple data (SIMD) execution engine |
January 31, 2012 |
| A mechanism is provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution |
| 8095777 |
Structure for predictive decoding |
January 10, 2012 |
| A design structure embodied in a machine readable medium used in a design process includes an apparatus for predictive decoding, the apparatus including register logic for fetching an instruction; predictor logic containing predictor information including prior instruction execution |
| 8030649 |
Scan testing in single-chip multicore systems |
October 4, 2011 |
| Various techniques for testing multicore processors in an integrated circuit. Each core includes a plurality of registers configured to form at least two scan chains. In one embodiment, a verification unit located in the integrated circuit is electrically coupled to outputs of the scan |
| 8010953 |
Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine |
August 30, 2011 |
| Performing scalar operations using a SIMD data parallel execution unit is provided. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar |
| 7977965 |
Soft error detection for latches |
July 12, 2011 |
| A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided to the latch and |
| 7900025 |
Floating point only SIMD instruction set architecture including compare, select, Boolean, and al |
March 1, 2011 |
| Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The |
| 7877759 |
System for efficient performance monitoring of a large number of simultaneous events |
January 25, 2011 |
| A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count |
| 7877582 |
Multi-addressable register file |
January 25, 2011 |
| A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instruc |
| 7865693 |
Aligning precision converted vector data using mask indicating offset relative to element bounda |
January 4, 2011 |
| Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector eleme |
| 7849294 |
Sharing data in internal and memory representations with dynamic data-driven conversion |
December 7, 2010 |
| Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whethe |
| 7849293 |
Method and structure for low latency load-tagged pointer instruction for computer microarchitech |
December 7, 2010 |
| A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction |
| 7836260 |
Low complexity speculative multithreading system based on unmodified microprocessor core |
November 16, 2010 |
| A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memo |
| 7797521 |
Method, system, and computer program product for path-correlated indirect address predictions |
September 14, 2010 |
| A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits i |
| 7620756 |
Method and apparatus for updating wide storage array over a narrow bus |
November 17, 2009 |
| A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m<n) for updating a wide data storage array. The apparatus includes: a staging latch accommodating m bits, e.g., 32 bits; control circuitry for depositing the m bits of data from a data b |
| 7512745 |
Method for garbage collection in heterogeneous multiprocessor systems |
March 31, 2009 |
| Garbage collection in heterogeneous multiprocessor systems is provided. In some illustrative embodiments, garbage collection operations are distributed across a plurality of the processors in the heterogeneous multiprocessor system. Portions of a global mark queue are assigned to pro |
| 7461383 |
Method and apparatus for efficient performance monitoring of a large number of simultaneous even |
December 2, 2008 |
| A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count |
| 7404041 |
Low complexity speculative multithreading system based on unmodified microprocessor core |
July 22, 2008 |
| A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memo |
| 7134028 |
Processor with low overhead predictive supply voltage gating for leakage power reduction |
November 7, 2006 |
| An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off |
| 7051255 |
Method and apparatus for reducing power dissipation in latches during scan operation |
May 23, 2006 |
| A method and apparatus for reducing power dissipation during a scan operation during testing of digital logic circuits which provides for scanning data while switching a limited number of nodes during scan-in and scan-out of input and result chains, and which isolates the logic circu |
