| Patent Number |
Title Of Patent |
Date Issued |
| 7560792 |
Reliable high voltage gate dielectric layers using a dual nitridation process |
July 14, 2009 |
| Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) |
| 7553718 |
Methods, systems and structures for forming semiconductor structures incorporating high-temperat |
June 30, 2009 |
| A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embod |
| 7244654 |
Drive current improvement from recessed SiGe incorporation close to gate |
July 17, 2007 |
| A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed |
| 7226834 |
PMD liner nitride films and fabrication methods for improved NMOS performance |
June 5, 2007 |
| Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the |
| 7192894 |
High performance CMOS transistors using PMD liner stress |
March 20, 2007 |
| A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting |
| 7183165 |
Reliable high voltage gate dielectric layers using a dual nitridation process |
February 27, 2007 |
| Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) |
| 6933248 |
Method for transistor gate dielectric layer with uniform nitrogen concentration |
August 23, 2005 |
| The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N.sub.2 O which redistributes the incorporated species t |
| 6737354 |
Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide f |
May 18, 2004 |
| An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide and/or cap oxide from the PMOS gate areas before doing PMOS implanting steps(K and M). The ca |
| 6737333 |
Semiconductor device isolation structure and method of forming |
May 18, 2004 |
| A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion |
| 6709938 |
Source/drain extension fabrication process with direct implantation |
March 23, 2004 |
| An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without an oxide layer (step D2), covering the gates with a cap oxide layer(step E2), covering NMOS devices with photoresist(step F2), |
| 6699763 |
Disposable spacer technology for reduced cost CMOS processing |
March 2, 2004 |
| A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type sourc |
| 6645840 |
Multi-layered polysilicon process |
November 11, 2003 |
| A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate structure after thermal oxid |
| 6632747 |
Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile |
October 14, 2003 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to c |
| 6632718 |
Disposable spacer technology for reduced cost CMOS processing |
October 14, 2003 |
| A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type sourc |
| 6548366 |
Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile |
April 15, 2003 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer |
| 6503846 |
Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor g |
January 7, 2003 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer |
| 6326281 |
Integrated circuit isolation |
December 4, 2001 |
| Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate. |
| 6242295 |
Method of fabricating a shallow doped region for a shallow junction transistor |
June 5, 2001 |
| A method of forming a plurality of shallow junction transistors, the method comprising the steps of providing a substrate (10) having a first region (13) and a second region (15). The first region (13) and the second region (15) include a first channel region (14) and a second channel re |
| 6136654 |
Method of forming thin silicon nitride or silicon oxynitride gate dielectrics |
October 24, 2000 |
| An embodiment of the instant invention is a method of forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface; forming an oxygen-containing layer (layer 14) on the semiconductor substrate; and |
| 6093659 |
Selective area halogen doping to achieve dual gate oxide thickness on a wafer |
July 25, 2000 |
| A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is desired. These areas are then |
| 6087268 |
Method to reduce boron diffusion through gate oxide using sidewall spacers |
July 11, 2000 |
| A gate electrode of a MOS transistor wherein gate oxide 12 is placed over substrate 10. Boron-doped polysilicon gate electrode 14 is placed over gate oxide 12. Optionally, drain extender implants may be added to substrate 10. Low-temperature-deposited nitride layer 18 is placed over |
| 6063670 |
Gate fabrication processes for split-gate transistors |
May 16, 2000 |
| A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first gate dielectric (20). The di |
| 6030874 |
Doped polysilicon to retard boron diffusion into and through thin gate dielectrics |
February 29, 2000 |
| An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconduct |
| 5717238 |
Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a bo |
February 10, 1998 |
| A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or |
| 5585286 |
Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce cha |
December 17, 1996 |
| A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or |
