| Patent Number |
Title Of Patent |
Date Issued |
| 7574537 |
Method, apparatus, and computer program product for migrating data pages by disabling selected D |
August 11, 2009 |
| A method, apparatus, and computer program product are disclosed in a data processing system for migrating data pages subject to DMA access by temporarily disabling selected DMA operations within a physical I/O adapter. A determination is made as to whether to disable data access DMA |
| 7555002 |
Infiniband general services queue pair virtualization for multiple logical ports on a single phy |
June 30, 2009 |
| An aliased queue pair is provided within a logically partitioned data processing system for each logical partition for the single general services management queue pair that exists within a physical host channel adapter. Packets intended for the logical ports are received at the phys |
| 7428598 |
Infiniband multicast operation in an LPAR environment |
September 23, 2008 |
| A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A pref |
| 7283473 |
Apparatus, system and method for providing multiple logical channel adapters within a single phy |
October 16, 2007 |
| An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter |
| 7149220 |
System, method, and product for managing data transfers in a network |
December 12, 2006 |
| A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to tra |
| 7099955 |
End node partitioning using LMC for a system area network |
August 29, 2006 |
| A method for routing System Area Network (SAN) packets to multiple partitions within a single end node is provided. A range of Local Identification addresses (LIDs) are assigned to a channel adapter port within the SAN. Lower order bits within the LID are then assigned to select the |
| 7093024 |
End node partitioning using virtualization |
August 15, 2006 |
| A mechanism for allowing a single physical IB node to virtualize a plurality of host channel adapters is provided. This includes providing the appearance of both a router and multiple virtual HCA's residing behind that router, to the external REAL subnet components. Each virtual host |
| 7092401 |
Apparatus and method for managing work and completion queues using head and tail pointers with e |
August 15, 2006 |
| An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. Reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the hos |
| 7010633 |
Apparatus, system and method for controlling access to facilities based on usage classes |
March 7, 2006 |
| An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With t |
| 6938138 |
Method and apparatus for managing access to memory |
August 30, 2005 |
| A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being |
| 6834332 |
APPARATUS AND METHOD FOR SWAPPING-OUT REAL MEMORY BY INHIBITING I/O OPERATIONS TO A MEMORY REGIO |
December 21, 2004 |
| An apparatus and method for swapping out real memory by inhibiting input/output (I/O) operations to a memory region are provided. The apparatus and method provide a mechanism in which a quiesce indicator is provided in a field containing the current outstanding I/O count associated w |
| 6789143 |
Infiniband work and completion queue management via head and tail circular buffers with indirect |
September 7, 2004 |
| A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a me |
| 6748499 |
Sharing memory tables between host channel adapters |
June 8, 2004 |
| A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the |
| 6725296 |
Apparatus and method for managing work and completion queues using head and tail pointers |
April 20, 2004 |
| An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter |
| 6721335 |
Segment-controlled process in a link switch connected between nodes in a multiple node network f |
April 13, 2004 |
| Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A common link switch is used in a network to connect links to all nodes, the segment structures in each message is preserved when |
| 6691217 |
Method and apparatus for associating memory windows with memory regions in a data storage system |
February 10, 2004 |
| A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address |
| 6665809 |
Digital frequency correction |
December 16, 2003 |
| The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of tim |
| 6601148 |
Infiniband memory windows management directly in hardware |
July 29, 2003 |
| A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A se |
| 6578122 |
Using an access key to protect and point to regions in windows for infiniband |
June 10, 2003 |
| A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate |
| 6570885 |
Segment-controlled process for controlling castouts from a communication cache in a port in any |
May 27, 2003 |
| Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A port cache of the destination node of each transmitted message obtains a message control block (MCB) which is used to control th |
| 6188675 |
System and method for self-identifying and configuring the nodes of a network |
February 13, 2001 |
| A system and method for progressively identifying and configuring the nodes of a network having an unknown or partially unknown topology are presented. A special all-node address indicator is designated for insertion in a packet to be sent from a given node with known node address to |
| 5948060 |
Speeding-up communication rates on links transferring data structures by a method of handing sca |
September 7, 1999 |
| Speeds up a commanded system to read or write data for a large number of data frames transmitted on a link by executing a TRANSFER STRUCTURE instruction that automatically controls the reading or writing of a large number of scattered storage blocks in the storage of the commanded system |
| 5944797 |
Data mover hardware controlled processing in a commanding system and in a commanded system for c |
August 31, 1999 |
| The present invention significantly reduces or eliminates the involvment of central processors in the message block handling of received communication-link responses within a Central Processing Complex (CPC). When a commanding system sends a command, it must receive a response frame |
| 5938786 |
Simplified recovery of damaged frames in a communication link |
August 17, 1999 |
| An apparatus and method is provided for asynchronously transmitting data across fiber optical cables in a serial manner. Frames are provided as a mechanism to transmit associated data over a serial link and to tie the data being transmitted to a particular buffer set. Each outstanding |
| 5706432 |
Mechanism for receiving messages at a coupling facility |
January 6, 1998 |
| Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is acces |
| 5680575 |
Interconnect failure detection and cache reset apparatus |
October 21, 1997 |
| A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first |
| 5651033 |
Inter-system data communication channel comprised of parallel electrical conductors that simulat |
July 22, 1997 |
| A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along wit |
