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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Goth; George R.
Address:
Poughkeepsie, NY
No. of patents:
21
Patents:












Patent Number Title Of Patent Date Issued
6967375 Reduction of chemical mechanical planarization (CMP) scratches with sacrificial dielectric polis November 22, 2005
Disclosed in a method of planarizing a silicon on insulator (SOI) structure. The invention performs a first chemical mechanical planarization (CMP) process on an insulator (e.g., oxide) layer. However, this first CMP process creates scratches on the insulator layer. The invention for
6518145 Methods to control the threshold voltage of a deep trench corner device February 11, 2003
A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the
6021360 Process controller for balancing usage of tool sets February 1, 2000
A system monitors usage of a tool in a tool set and warns an operator and/or prevents usage of a tool chosen by an operator, subject to possible override by the operator, if permitted, in order to balance usage among tools of the tool set and verify operational conditions of tools of the
5976982 Methods for protecting device components from chemical mechanical polish induced defects November 2, 1999
A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilico
4824797 Self-aligned channel stop April 25, 1989
Disclosed is a process of forming channel stops which starts with a, for example, N type silicon substrate having on the surface thereof an insulator trench mask defining the region of silicon where an isolation trench is desired. A blockout layer having an opening in correspondence
4758528 Self-aligned metal process for integrated circuit metallization July 19, 1988
A method of forming on a substrate a pattern of structures having a thickness on the order of one micron or less. A first insulating layer is formed on a major surface of a substrate, for example, a silicon body. A polycrystalline silicon layer is formed thereover and openings are formed
4743565 Lateral device structures using self-aligned fabrication techniques May 10, 1988
Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from a
4719185 Method of making shallow junction complementary vertical bipolar transistor pair January 12, 1988
Disclosed is a complementary vertical NPN and PNP pair having matched performance. The PNP collector is located deep in an epitaxial layer overlying a semiconductor substrate. The junction depths and surface concentrations of both emitters are quite similar; the junction depths and s
4717678 Method of forming self-aligned P contact January 5, 1988
Disclosed is a process for forming self-aligned low resistance ohmic contact to a P doped region (e.g., base of an NPN device) in conjunction with forming similar contact to a (highly) N doped region (e.g., emitter of NPN). After forming a P doped region in an N type monocrystalline
4704368 Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic November 3, 1987
A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-sh
4691219 Self-aligned polysilicon base contact structure September 1, 1987
An integrated bipolar transistor having a self-aligned polysilicon base contact is formed by depositing a first doped polysilicon layer and a silicon nitride passivating layer on the surface of a semiconductor substrate having an isolated collector region therein. An opening is forme
4688073 Lateral device structures using self-aligned fabrication techniques August 18, 1987
Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from a
4665007 Planarization process for organic filling of deep trenches May 12, 1987
Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low dens
4608589 Self-aligned metal structure for integrated circuits August 26, 1986
A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness
4589193 Metal silicide channel stoppers for integrated circuits and method for making the same May 20, 1986
Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly in
4549927 Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal s October 29, 1985
Deep trenches (14,15) are formed according to the desired pattern through the N epitaxial layer (13) and N.sup.+ subcollector region (12) into the P.sup.- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa
4541168 Method for making metal contact studs between first level metal and regions of a semiconductor d September 17, 1985
The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent
4534826 Trench etch process for dielectric isolation August 13, 1985
A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls by precluding significant variation in etch bias during the trench formation.
4508579 Lateral device structures using self-aligned fabrication techniques April 2, 1985
Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from a
4400865 Self-aligned metal process for integrated circuit metallization August 30, 1983
A self-aligned metal process is decribed which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of
4151010 Forming adjacent impurity regions in a semiconductor by oxide masking April 24, 1979
A method for forming adjacent impurity regions of differing conductivities in a semiconductor substrate without using lithography. N type impurities of a first conductivity are introduced into the substrate to form first impurity regions. The substrate is then oxidized to create a mask h










 
 
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