Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Goodnow; Kenneth J.
Address:
Essex Junction, VT
No. of patents:
62
Patents:


1 2










Patent Number Title Of Patent Date Issued
8575964 Inactivity triggered self clocking logic family November 5, 2013
Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the l
8301921 Secondary power utilization during peak power times October 30, 2012
The invention generally relates to the utilization of electric power, and more particularly to systems and methods for selectively utilizing secondary power sources during peak power times. A method includes receiving a notification of a peak power time, and discontinuing use of a pr
8291357 On-chip identification circuit incorporating pairs of conductors, each having an essentially ran October 16, 2012
Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip
8174329 Power management architecture and method of modulating oscillator frequency based on voltage sup May 8, 2012
A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an ind
8132136 Dynamic critical path detector for digital logic circuit paths March 6, 2012
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further include
8122273 Structure and method to optimize computational efficiency in low-power environments February 21, 2012
A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficienc
8055925 Structure and method to optimize computational efficiency in low-power environments November 8, 2011
A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plur
8020137 Structure for an on-demand power supply current modification system for an integrated circuit September 13, 2011
A design structure for a circuit that selectively connects an integrated circuit to elements external to the integrated circuits. The circuit includes and input/output element that selectively connects an input/output pin as a function of a power requirement or a signal bandwidth req
8010813 Structure for system for extending the useful life of another system August 30, 2011
Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devic
7949978 Structure for system architectures for and methods of scheduling on-chip and across-chip noise e May 24, 2011
A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are
7941772 Dynamic critical path detector for digital logic circuit paths May 10, 2011
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further include
7913193 Determining relative amount of usage of data retaining device based on potential of charge stori March 22, 2011
An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a cha
7903493 Design structure for estimating and/or predicting power cycle length, method of estimating and/o March 8, 2011
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals o
7869298 Determining relative amount of usage of data retaining device based on potential of charge stori January 11, 2011
A system for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data
7865789 System and method for system-on-chip interconnect verification January 4, 2011
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator
7849426 Mechanism for detection and compensation of NBTI induced threshold degradation December 7, 2010
The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and
7823017 Structure for task based debugger (transaction-event-job-trigger) October 26, 2010
Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structu
7793163 Method and system for extending the useful life of another system September 7, 2010
Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate
7791968 Determining history state of data in data retaining device based on state of partially depleted September 7, 2010
An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device
7750670 System and method for dynamically executing a function in a programmable logic array July 6, 2010
A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between
7633819 Determining history state of data in data retaining device based on state of partially depleted December 15, 2009
A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device.
7594140 Task based debugger (transaction-event-job-trigger) September 22, 2009
The embodiments of the invention provide an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an
7579897 Design structure for implementing oxide leakage based voltage divider network for integrated cir August 25, 2009
A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configu
7545165 System architectures for and methods of scheduling on-chip and across-chip noise events in an in June 9, 2009
Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodi
7519941 Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for April 14, 2009
Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple m
7512813 Method for system level protection of field programmable logic devices March 31, 2009
A method for protecting a dynamically reconfigurable computing system includes generating an encoding key and passing the encoding key, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library
7504847 Mechanism for detection and compensation of NBTI induced threshold degradation March 17, 2009
The embodiments of the invention provide an apparatus and method for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate
7489163 FPGA powerup to known functional state February 10, 2009
A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA de
7460422 Determining history state of data based on state of partially depleted silicon-on-insulator December 2, 2008
A system for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD S
7437620 Method and system for extending the useful life of another system October 14, 2008
Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate
7417453 System and method for dynamically executing a function in a programmable logic array August 26, 2008
A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The
7397718 Determining relative amount of usage of data retaining device based on potential of charge stori July 8, 2008
A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In
7313738 System and method for system-on-chip interconnect verification December 25, 2007
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator
7307467 Structure and method for implementing oxide leakage based voltage divider network for integrated December 11, 2007
A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of
7304493 FPGA powerup to known functional state December 4, 2007
A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device wou
7302605 Method and structure for replacing faulty operating code contained in a ROM for a processor November 27, 2007
The invention provides replacement operation code for specific defective lines of operation code contained in a ROM often on an ASIC chip which code is used in a processor. ROM memory constitutes the best use of chip space and is the most economical to manufacture of all of the various
7282949 FPGA powerup to known functional state October 16, 2007
A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device wou
7249279 Multiprocessor code fix using a local cache July 24, 2007
Operating code fixes are supplied to multiple processors utilizing the same operating code by storing the correction code fixes in a central RAM, and distributing the code fixes over a dedicated code fix bus to a local cache for each processor. The first processor encountering a code
7248838 Wireless communication system within a system on a chip July 24, 2007
A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from
7222248 Method of switching voltage islands in integrated circuits when a grid voltage at a reference lo May 22, 2007
An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage isl
7139881 Semiconductor device comprising a plurality of memory structures November 21, 2006
A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each
7134104 Method of selectively building redundant logic structures to improve fault tolerance November 7, 2006
A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL
7129821 Communication systems and methods using microelectronics power distribution network October 31, 2006
A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to
7107469 Power down processing islands September 12, 2006
A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a
7103320 Wireless communication system within a system on a chip September 5, 2006
A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly re
6954085 System and method for dynamically executing a function in a programmable logic array October 11, 2005
A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The
6825711 Power reduction by stage in integrated circuit November 30, 2004
An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages ca
6802033 Low-power critical error rate communications controller October 5, 2004
A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is ente
6658634 Logic power optimization algorithm December 2, 2003
Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then insertin
6604174 Performance based system and method for dynamic allocation of a unified multiport cache August 5, 2003
The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle look ups through a multiport tag and multiple single-cycle cache accesses from a multiport
1 2










 
 
  Recently Added Patents
Fuel-based injection control
Support core for cold shrink tube
Insulated container sleeve
System and method for seamlessly increasing download throughput
System and method for configuring a direct lift control system of a vehicle
Enhancement of semiconducting photovoltaic absorbers by the addition of alkali salts through solution coating techniques
Print system
  Randomly Featured Patents
Disk drive having a crash stop detent actuator latch
Grill brush with lateral bristles
Closed tool bag
Timing signal recording system of a magnetic disk apparatus
Method for fabricating a semiconductor device
Lawn mower drive and control systems
Internal-combustion engine having an oil return system
Flash device
Relay
Migrating a network to tunnel-less encryption