| Patent Number |
Title Of Patent |
Date Issued |
| 6704856 |
Method for compacting an instruction queue |
March 9, 2004 |
| A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each r |
| 5890201 |
Content addressable memory having memory cells storing don't care states for address translation |
March 30, 1999 |
| A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the |
| 5784709 |
Translating buffer and method for translating addresses utilizing invalid and don't care states |
July 21, 1998 |
| A translation buffer and method for translating a virtual address to a physical address are disclosed. The translation buffer includes a plurality of storage locations, each including a tag store for storing a virtual page number and a data store for storing an associated physical pa |
| 5568415 |
Content addressable memory having a pair of memory cells storing don't care states for address t |
October 22, 1996 |
| A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors conne |
