| Patent Number |
Title Of Patent |
Date Issued |
| 6286090 |
Mechanism for selectively imposing interference order between page-table fetches and correspondi |
September 4, 2001 |
| A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flo |
| 6209065 |
Mechanism for optimizing generation of commit-signals in a distributed shared-memory system |
March 27, 2001 |
| A mechanism optimizes the generation of a commit-signal by control logic of the multiprocessor system in response to a memory reference operation issued by a processor to a local node of a multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes. The |
| 6108737 |
Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system |
August 22, 2000 |
| A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memo |
| 6088771 |
Mechanism for reducing latency of memory barrier operations on a multiprocessor system |
July 11, 2000 |
| A technique reduces the latency of a memory barrier (MB) operation used to impose an inter-reference order between sets of memory reference operations issued by a processor to a multiprocessor system having a shared memory. The technique comprises issuing the MB operation immediately |
| 6085263 |
Method and apparatus for employing commit-signals and prefetching to maintain inter-reference or |
July 4, 2000 |
| An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which |
| 6055605 |
Technique for reducing latency of inter-reference ordering using commit signals in a multiproces |
April 25, 2000 |
| A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inh |
| 5933598 |
Method for sharing variable-grained memory of workstations by sending particular block including |
August 3, 1999 |
| In a distributed shared memory system, workstations are connected to each other by a network. Each workstation includes a processor, a memory having addresses, and an input/output interface to interconnect the workstations. A software implemented method enables data sharing between the |
| 5787480 |
Lock-up free data sharing |
July 28, 1998 |
| A software implemented method for lock-up free data sharing operates in a networked computer system including a plurality of workstations. Each workstation including a processor, a memory having addresses, and an input/output interface connected to each other by a bus. A set of addre |
