| Patent Number |
Title Of Patent |
Date Issued |
| 7523016 |
Detecting anomalies |
April 21, 2009 |
| In general, systems and methods for identifying anomalous activity are described. For example, systems and methods are described, in which patterns of unusual behavior can be identified by aggregating logged, or sampled, data into cells and annotating each cell with statistically der |
| 7502895 |
Techniques for reducing castouts in a snoop filter |
March 10, 2009 |
| Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops |
| 7467131 |
Method and system for query data caching and optimization in a search engine system |
December 16, 2008 |
| When searching a document database in response to a search query, a determination is made as to whether a query result corresponding to the search query is stored in a cache. When the query result is stored in the cache, a reuse count for the search query is accessed. When predefined |
| 7389389 |
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-m |
June 17, 2008 |
| A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory l |
| 7254580 |
System and method for selectively searching partitions of a database |
August 7, 2007 |
| When a search query is received, a plurality of partition indexes are searched using the set of search terms in the search query. Each partition index corresponds to a partition of a document index. The search of each respective partition index identifies a subset of a plurality of d |
| 7174346 |
System and method for searching an extended database |
February 6, 2007 |
| Once a search query is received from a user, a standard index is searched based on the search query. The standard index forms part of a set of replicated standard indexes having multiple instances of the standard index. A signal is then determined based on the search of the standard |
| 7152191 |
Fault containment and error recovery in a scalable multiprocessor |
December 19, 2006 |
| A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a fa |
| 6988170 |
Scalable architecture based on single-chip multiprocessing |
January 17, 2006 |
| A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect |
| 6925537 |
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes |
August 2, 2005 |
| A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor c |
| 6918015 |
Scalable directory based cache coherence protocol |
July 12, 2005 |
| A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the |
| 6912624 |
Method and system for exclusive two-level caching in a chip-multiprocessor |
June 28, 2005 |
| To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache |
| 6751720 |
Method and system for detecting and resolving virtual address synonyms in a two-level cache hier |
June 15, 2004 |
| L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state ("Dtags") are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all poss |
| 6751710 |
Scalable multiprocessor system and cache coherence method |
June 15, 2004 |
| The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a |
| 6748498 |
Scalable multiprocessor system and cache coherence method implementing store-conditional memory |
June 8, 2004 |
| A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transact |
| 6738868 |
System for minimizing directory information in scalable multiprocessor systems with logically in |
May 18, 2004 |
| A system of scalable shared-memory multiprocessors includes processor nodes and I/O nodes. The I/O nodes connect I/O devices directly to an interconnection network of a system of scalable shared-memory multiprocessors. Each node of the system includes an interface to a local memory s |
| 6725343 |
System and method for generating cache coherence directory entries and error correction codes in |
April 20, 2004 |
| Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in |
| 6725334 |
Method and system for exclusive two-level caching in a chip-multiprocessor |
April 20, 2004 |
| To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache |
| 6697919 |
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-m |
February 24, 2004 |
| A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory l |
| 6678840 |
Fault containment and error recovery in a scalable multiprocessor |
January 13, 2004 |
| A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failur |
| 6675265 |
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes |
January 6, 2004 |
| A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor c |
| 6668308 |
Scalable architecture based on single-chip multiprocessing |
December 23, 2003 |
| A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect |
| 6640287 |
Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty request |
October 28, 2003 |
| An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimize |
| 6636949 |
System for handling coherence protocol races in a scalable shared memory system based on chip mu |
October 21, 2003 |
| In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol |
| 6633960 |
Scalable directory based cache coherence protocol |
October 14, 2003 |
| A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the |
| 6622218 |
Cache coherence protocol engine and method for efficient processing of interleaved memory transa |
September 16, 2003 |
| The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock perio |
| 6622217 |
Cache coherence protocol engine system and method for processing memory transaction in distinct |
September 16, 2003 |
| The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock perio |
| 6412056 |
Extended translation lookaside buffer with fine-grain state bits |
June 25, 2002 |
| A software distributed shared memory system includes a translation lookaside buffer extended to include fine-grain memory block-state bits associated with each block of information within a page stored in memory. The block-state bits provide multiple block states for each block. The |
| 5950228 |
Variable-grained memory sharing for clusters of symmetric multi-processors using private and sha |
September 7, 1999 |
| In a distributed shared memory system, clusters of symmetric multi-processors are connected to each other by a network. Each symmetric multi-processor includes a plurality of processors, a memory having addresses, and an input/output interface to interconnect the processors. A softwa |
