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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Gelman; Anatoly
Address:
San Diego, CA
No. of patents:
7
Patents:












Patent Number Title Of Patent Date Issued
8171260 Fetching all or portion of instructions in memory line up to branch instruction based on branch May 1, 2012
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a "block" of in
8170146 Radio frequency integrated circuit having frequency dependent noise mitigation with spectrum spr May 1, 2012
A plurality of baseband clock signals by detecting an interference condition associated with at least one of the plurality of baseband clock signals and by spreading the spectrum of the at least one of the plurality of baseband clock signals when the interference condition is detecte
7917790 Separate power island for high performance processor that reboots to second boot sector March 29, 2011
Separate power island for high performance processor. A multi-processor design is presented in which each of the processors is implemented in separately powered portions of a circuitry (e.g., an integrated circuit). One of the processors can be a main application processor, and another o
7787569 Radio frequency integrated circuit having frequency dependent noise mitigation with spectrum spr August 31, 2010
A radio frequency integrated circuit (RFIC) includes a low noise amplifier that amplifies an inbound radio frequency (RF) signal to produce an amplified RF signal. A down conversion module converts the amplified RF signal to a down converted signal based on a local oscillation. An analog
7552314 Fetching all or portion of instructions in memory line up to branch instruction based on branch June 23, 2009
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a "block" of in
6957327 Block-based branch target buffer October 18, 2005
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a "block" of in
6581138 Branch-prediction driven instruction prefetch June 17, 2003
The invention provides a method and apparatus for optimizing instruction prefetch and caching in a processor. In the preferred embodiment, a path prediction circuit maintains information about which cache lines are likely to be executed in the future. This information is used to inde










 
 
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