| Patent Number |
Title Of Patent |
Date Issued |
| 7625792 |
Method of base formation in a BiCMOS process |
December 1, 2009 |
| Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above t |
| 7538004 |
Method of fabrication for SiGe heterojunction bipolar transistor (HBT) |
May 26, 2009 |
| A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions inc |
| 7491985 |
Method of collector formation in BiCMOS technology |
February 17, 2009 |
| A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT |
| 7390721 |
Methods of base formation in a BiCMOS process |
June 24, 2008 |
| Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is i |
| 7317215 |
SiGe heterojunction bipolar transistor (HBT) |
January 8, 2008 |
| A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions inc |
| 7247924 |
Method of controlling grain size in a polysilicon layer and in semiconductor devices having poly |
July 24, 2007 |
| A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such tha |
| 7002190 |
Method of collector formation in BiCMOS technology |
February 21, 2006 |
| A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT |
| 6967167 |
Silicon dioxide removing method |
November 22, 2005 |
| A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds |
| 6965133 |
Method of base formation in a BiCMOS process |
November 15, 2005 |
| Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is i |
| 6936509 |
STI pull-down to control SiGe facet growth |
August 30, 2005 |
| A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a |
| 6911681 |
Method of base formation in a BiCMOS process |
June 28, 2005 |
| Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above t |
| 6682992 |
Method of controlling grain size in a polysilicon layer and in semiconductor devices having poly |
January 27, 2004 |
| A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such tha |
| 6674102 |
Sti pull-down to control SiGe facet growth |
January 6, 2004 |
| A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a |
| 6660664 |
Structure and method for formation of a blocked silicide resistor |
December 9, 2003 |
| A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film. |
| 6541336 |
Method of fabricating a bipolar transistor having a realigned emitter |
April 1, 2003 |
| A method of fabricating a bipolar transistor. The method comprising: forming an emitter opening in a dielectric layer to expose a surface of a base layer; performing a clean of the exposed surface, the clean removing any oxide present on the surface and passivating the surface to inhibit |
| 6448124 |
Method for epitaxial bipolar BiCMOS |
September 10, 2002 |
| A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; ( |
| 5635419 |
Porous silicon trench and capacitor structures |
June 3, 1997 |
| The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porou |
| 5508542 |
Porous silicon trench and capacitor structures |
April 16, 1996 |
| The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porou |
| 5356837 |
Method of making epitaxial cobalt silicide using a thin metal underlayer |
October 18, 1994 |
| An epitaxial cobalt silicide film is formed using a thin metal underlayer, which is placed underneath a cobalt layer prior to a heating step which forms the silicide film. More specifically, a refractory metal layer comprising tungsten, chromium, molybdenum, or a silicide thereof, is |
