| Patent Number |
Title Of Patent |
Date Issued |
| 6219773 |
System and method of retiring misaligned write operands from a write buffer |
April 17, 2001 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 6138230 |
Processor with multiple execution pipelines using pipe stage state information to control indepe |
October 24, 2000 |
| A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions |
| 5963984 |
Address translation unit employing programmable page size |
October 5, 1999 |
| Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside buffers. Selective comparisons between contents on a linear address bus and linear address tags a |
| 5907860 |
System and method of retiring store data from a write buffer |
May 25, 1999 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5835949 |
Method of identifying and self-modifying code |
November 10, 1998 |
| A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction |
| 5752274 |
Address translation unit employing a victim TLB |
May 12, 1998 |
| An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large a |
| 5664149 |
Coherency for write-back cache in a system designed for write-through cache using an export/inva |
September 2, 1997 |
| A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL proto |
| 5644741 |
Processor with single clock decode architecture employing single microROM |
July 1, 1997 |
| A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memor |
| 5615402 |
Unified write buffer having information identifying whether the address belongs to a first write |
March 25, 1997 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5584009 |
System and method of retiring store data from a write buffer |
December 10, 1996 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
| 5471598 |
Data dependency detection and handling in a microprocessor with write buffer |
November 28, 1995 |
| A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to |
