| Patent Number |
Title Of Patent |
Date Issued |
| 7558945 |
System and method for register renaming |
July 7, 2009 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 7555631 |
RISC microprocessor architecture implementing multiple typed register sets |
June 30, 2009 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 7430651 |
System and method for assigning tags to control instruction processing in a superscalar processo |
September 30, 2008 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for ta |
| 7043624 |
System and method for assigning tags to control instruction processing in a superscalar processo |
May 9, 2006 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for ta |
| 6970995 |
System and method for register renaming |
November 29, 2005 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 6922772 |
System and method for register renaming |
July 26, 2005 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 6757808 |
System and method for assigning tags to control instruction processing in a superscalar processo |
June 29, 2004 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for taggin |
| 6408375 |
System and method for register renaming |
June 18, 2002 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 6360309 |
System and method for assigning tags to control instruction processing in a superscalar processo |
March 19, 2002 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for taggin |
| 6272617 |
System and method for register renaming |
August 7, 2001 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 6138231 |
System and method for register renaming |
October 24, 2000 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 6092176 |
System and method for assigning tags to control instruction processing in a superscalar processo |
July 18, 2000 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for taggin |
| 5896542 |
System and method for assigning tags to control instruction processing in a superscalar processo |
April 20, 1999 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for taggin |
| 5892963 |
System and method for assigning tags to instructions to control instruction execution |
April 6, 1999 |
| Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots conta |
| 5838986 |
RISC microprocessor architecture implementing multiple typed register sets |
November 17, 1998 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 5809276 |
System and method for register renaming |
September 15, 1998 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 5682546 |
RISC microprocessor architecture implementing multiple typed register sets |
October 28, 1997 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 5628021 |
System and method for assigning tags to control instruction processing in a superscalar processo |
May 6, 1997 |
| A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for taggin |
| 5604912 |
System and method for assigning tags to instructions to control instruction execution |
February 18, 1997 |
| Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots conta |
| 5590295 |
System and method for register renaming |
December 31, 1996 |
| A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a |
| 5560035 |
RISC microprocessor architecture implementing multiple typed register sets |
September 24, 1996 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 5493687 |
RISC microprocessor architecture implementing multiple typed register sets |
February 20, 1996 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
