| Patent Number |
Title Of Patent |
Date Issued |
| 6979878 |
Isolation structure having implanted silicon atoms at the top corner of the isolation trench fil |
December 27, 2005 |
| A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of |
| 6911707 |
Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor |
June 28, 2005 |
| An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, |
| 6767794 |
Method of making ultra thin oxide formation using selective etchback technique integrated with t |
July 27, 2004 |
| A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by |
| 6743688 |
High performance MOSFET with modulated channel gate thickness |
June 1, 2004 |
| A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by |
| 6727569 |
Method of making enhanced trench oxide with low temperature nitrogen integration |
April 27, 2004 |
| A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the |
| 6674135 |
Semiconductor structure having elevated salicided source/drain regions and metal gate electrode |
January 6, 2004 |
| A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions |
| 6661061 |
Integrated circuit with differing gate oxide thickness |
December 9, 2003 |
| A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen |
| 6661057 |
Tri-level segmented control transistor and fabrication method |
December 9, 2003 |
| A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. Afte |
| 6638829 |
Semiconductor structure having a metal gate electrode and elevated salicided source/drain region |
October 28, 2003 |
| A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode |
| 6603180 |
Semiconductor device having large-area silicide layer and process of fabrication thereof |
August 5, 2003 |
| A semiconductor device having a large-area silicide layer and fabrication method is provided. A semiconductor device, consistent with one embodiment of the invention, includes a silicon substrate, a gate insulating layer disposed over the silicon substrate, a gate electrode disposed over |
| 6552776 |
Photolithographic system including light filter that compensates for lens error |
April 22, 2003 |
| A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error |
| 6531364 |
Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilico |
March 11, 2003 |
| A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial |
| 6504218 |
Asymmetrical N-channel and P-channel devices |
January 7, 2003 |
| An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped |
| 6483157 |
Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in th |
November 19, 2002 |
| A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A silicon-based substrate is provided. A gate oxide layer is grown across the substrate. The gate oxide layer may be incorporated with barrier atoms bonded to silicon or oxygen |
| 6469316 |
Test structure to monitor the effects of polysilicon pre-doping |
October 22, 2002 |
| Various embodiments of a test circuit and methods of fabricating and using the same are provided. In one aspect, a test circuit includes a semiconductor substrate and a mask thereon that has an opening to enable impurity doping of selected portions of the test circuit. A plurality of |
| 6451657 |
Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant |
September 17, 2002 |
| A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the g |
| 6433400 |
Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolatio |
August 13, 2002 |
| A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of |
| 6429052 |
Method of making high performance transistor with a reduced width gate electrode and device comp |
August 6, 2002 |
| The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or "t-shaped" gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, forming a layer of polysilicon abov |
| 6420730 |
Elevated transistor fabrication technique |
July 16, 2002 |
| A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed |
| 6420220 |
Method of forming electrode for high performance semiconductor devices |
July 16, 2002 |
| A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method also includes forming a silici |
| 6417539 |
High density memory cell assembly and methods |
July 9, 2002 |
| A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielect |
| 6410967 |
Transistor having enhanced metal silicide and a self-aligned gate electrode |
June 25, 2002 |
| A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the m |
| 6410409 |
Implanted barrier layer for retarding upward diffusion of substrate dopant |
June 25, 2002 |
| Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of t |
| 6403445 |
Enhanced trench isolation structure |
June 11, 2002 |
| An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the |
| 6388298 |
Detached drain MOSFET |
May 14, 2002 |
| A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The |
| 6383874 |
In-situ stack for high volume production of isolation regions |
May 7, 2002 |
| A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing |
| 6383872 |
Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a |
May 7, 2002 |
| An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure th |
| 6380554 |
Test structure for electrically measuring the degree of misalignment between successive layers o |
April 30, 2002 |
| The present invention advantageously provides a test structure and method for using electrical measurements to determine the overlay between successive layers of conductors lithographically patterned upon a semiconductor topography. According to an embodiment, a test structure is pro |
| 6380055 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer |
April 30, 2002 |
| A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilico |
| 6373113 |
Nitrogenated gate structure for improved transistor performance and method for making same |
April 16, 2002 |
| An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each inclu |
| 6372588 |
Method of making an IGFET using solid phase diffusion to dope the gate, source and drain |
April 16, 2002 |
| A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device |
| 6365943 |
High density integrated circuit |
April 2, 2002 |
| A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor t |
| 6362510 |
Semiconductor topography having improved active device isolation and reduced dopant migration |
March 26, 2002 |
| A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surf |
| 6358828 |
Ultra high density series-connected transistors formed on separate elevational levels |
March 19, 2002 |
| A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form seri |
| 6355955 |
Transistor and a method for forming the transistor with elevated and/or relatively shallow sourc |
March 12, 2002 |
| An integrated circuit fabrication process is provided for forming a transistor having shallow effective source/drain regions and/or laterally shortened source/drain regions. In one embodiment a mesa is formed from the semiconductor substrate. The mesa preferably extends from an upper |
| 6326251 |
Method of making salicidation of source and drain regions with metal gate MOSFET |
December 4, 2001 |
| A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A sil |
| 6323561 |
Spacer formation for precise salicide formation |
November 27, 2001 |
| The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second s |
| 6323519 |
Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabri |
November 27, 2001 |
| A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. A conformal oxide having thickness between about 1 |
| 6309936 |
Integrated formation of LDD and non-LDD semiconductor devices |
October 30, 2001 |
| A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted |
| 6306763 |
Enhanced salicidation technique |
October 23, 2001 |
| A semiconductor fabrication process in which enhanced salicidation and reliability is achieved by implanting a silicon bearing species and a nitrogen bearing species into the source/drain regions and polysilicon regions of an integrated circuit transistor prior to the silicide format |
| 6303962 |
Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacri |
October 16, 2001 |
| A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysi |
| 6300661 |
Mutual implant region used for applying power/ground to a source of a transistor and a well of a |
October 9, 2001 |
| An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the |
| 6297535 |
Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier i |
October 2, 2001 |
| A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. |
| 6288432 |
Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressur |
September 11, 2001 |
| An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen he |
| 6281132 |
Device and method for etching nitride spacers formed upon an integrated circuit gate conductor |
August 28, 2001 |
| A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of |
| 6274442 |
Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making |
August 14, 2001 |
| An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably nitrogen atoms, within a barrier layer. The barrier layer is interposed between the gate dielectric and the semiconductor substrate. The barrier layer serves to inhibit the passage of do |
| 6268637 |
Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced C |
July 31, 2001 |
| An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulatin |
| 6268634 |
Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant |
July 31, 2001 |
| A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the g |
| 6265749 |
Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectri |
July 24, 2001 |
| A transistor is provided having a metal silicide gate spaced above a semiconductor substrate by a high-dielectric-constant ceramic gate dielectric. The entire gate conductor is preferably composed of a metal silicide. In an embodiment, the metal silicide is cobalt silicide and the ce |
| 6261909 |
Semiconductor device having ultra shallow junctions and a reduced channel length and method for |
July 17, 2001 |
| The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second |
