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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Garcia; Graham A.
Address:
San Diego, CA
No. of patents:
15
Patents:












Patent Number Title Of Patent Date Issued
H1423 Method for fabricating a silicon-on-insulator voltage multiplier April 4, 1995
The present invention provides a method for fabricating a silicon-on-insulator voltage multiplier. The method comprises the steps of: forming a first silicon layer having a first concentration of a first dopant with a first polarity on a silicon wafer having a second concentration of
6703647 Triple base bipolar phototransistor March 9, 2004
A high gain phototransistor uses lateral and vertical transistor structures and a triple base. The base regions of two vertical structures are in the bulk of a semiconductor substrate while the base of a single lateral structure is adjacent a light receiving phototransistor surface. Mino
6667711 Method and apparatus for discerning degradation of electromagnetic radiating tubes December 23, 2003
The invention is designed to employ one or a multitude of sensors designed to allow operational monitoring of any of a variety of electromagnetic radiating tubes. Monitoring is conducted to detect a degradation in performance which can be used as a factor in deciding whether tube rep
6165801 Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure December 26, 2000
A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized
6051846 Monolithic integrated high-T.sub.c superconductor-semiconductor structure April 18, 2000
A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized
5587597 Semiconductor-on-insulator device interconnects December 24, 1996
A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed direct
5521412 Low and high minority carrier lifetime layers in a single semiconductor structure May 28, 1996
A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer
5468674 Method for forming low and high minority carrier lifetime layers in a single semiconductor struc November 21, 1995
A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer
5253196 MOS analog memory with injection capacitors October 12, 1993
An integrated circuit memory element is capable of storing analog information. The memory value can be increased and decreased incrementally with no knowledge of the current state and may be stored for a long period of time. Analog memory information is stored as an electrical charge on
5196802 Method and apparatus for characterizing the quality of electrically thin semiconductor films March 23, 1993
A method and apparatus for characterizing the quality of an electrically thin semiconductor film and its interfaces with adjacent materials by employing a capacitor and a topside electrical contact on the same side of the electrically thin semiconductor film to thereby permit the taking
5066613 Process for making semiconductor-on-insulator device interconnects November 19, 1991
A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed direct
5027171 Dual polarity floating gate MOS analog memory device June 25, 1991
A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common
4843448 Thin-film integrated injection logic June 27, 1989
An integrated injection logic device formed on an insulating substrate. A lateral, load transistor and an adjacent, vertical switching transistor are formed in the semiconductor layer such that the collector region of the lateral transistor coincides with the base region of the switching
4725728 Fiber optical time delay resonant oscillating strain gauge February 16, 1988
Longitudinal tensile and/or compressive strain in optical fibers is detered by an entirely optical technique. A test optical fiber optically coupled to optical injection and extraction couplers form an optically recirculating loop. A semiconductor laser diode feeds a series of narrow
4510607 Semiconductor laser end-facet coatings for use in solid or liquid environments April 9, 1985
An improvement for a semiconductor laser allows the facet reflectivity to be modified to compensate for the presence of a liquid or transparent solid medium having an index of refraction n.sub.m. A first dielectric coating is disposed on an end-facet of the semiconductor laser and has an










 
 
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