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Inventor:
Fuller; Douglas A.
Address:
Eagan, MN
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
7562263 System and method for detecting and recovering from errors in a control store of an electronic d July 14, 2009
A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are detected and recovered from without any required interaction with an operating system of the
7478025 System and method to support dynamic partitioning of units to a shared resource January 13, 2009
A system and method for performing dynamic partitioning operations within a data processing system is disclosed. According to one embodiment, the current invention provides a system that allows an unit to be added to an executing data processing partition. The partition may include a sha
7356647 Cache with integrated capability to write out entire cache April 8, 2008
A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of
6751756 First level cache parity error inject June 15, 2004
A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable ind
6542985 Event counter April 1, 2003
A data processor is disclosed that executes a number of microcode instruction words. Each of the microcode instruction words has a bit field reserved to indicate which, if any, event counters are to be incremented. This enables the number of executions of a particular microcode instr
5819072 Method of using a four-state simulator for testing integrated circuit designs having variable ti October 6, 1998
Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and ide
5796972 Method and apparatus for performing microcode paging during instruction execution in an instruct August 18, 1998
Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the mi
5726903 Method and apparatus for resolving conflicts between cell substitution recommendations provided March 10, 1998
A method and apparatus for efficiently identifying and resolving conflicts between conflicting cell substitution recommendations. Unlike the prior art, the present invention provides a resolving means within a data processing system to identify and resolve conflicting cell substitution
5724250 Method and apparatus for performing drive strength adjust optimization in a circuit design March 3, 1998
A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route
5719783 Method and apparatus for performing timing analysis on a circuit design February 17, 1998
A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing viol
5432747 Self-timing clock generator for precharged synchronous SRAM July 11, 1995
A self-timing clock generator for use with a precharged Static Random Access Memory (SRAM). The invention asynchronously switches the memory clock pulse to a precharge signal upon recognition of completion of a memory access cycle. Recognition of completion of the memory access cycle










 
 
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