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Fukumoto; Katsumi
Nara, JP
No. of patents:

Patent Number Title Of Patent Date Issued
7187582 Erroneous operation preventing circuit of non-volatile memory device March 6, 2007
An erroneous operation preventing circuit of an electrically rewritable non-volatile memory device is for setting one or more operational modes of a plurality of operational modes including at least a first reading mode of reading out data from a memory array 4, a programming mode, an
7057922 Nonvolatile semiconductor memory device June 6, 2006
The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of
6865658 Nonvolatile data management system using data segments and link information March 8, 2005
A data management system and method use link information stored with a plurality of data segments. The data management system includes: a nonvolatile semiconductor storage section including a plurality of blocks; a storage control section; a data management system control section for
6370058 Non-volatile semiconductor memory device and system LSI including the same April 9, 2002
A non-volatile semiconductor memory device includes a memory cell array capable of storing data in volatile and non-volatile states, and a determination circuit for determining whether a row address in a current cycle is the same as that in a previous cycle. When the row address in the
6240032 Non-volatile semiconductor memory allowing user to enter various refresh commands May 29, 2001
In a non-volatile flash memory having memory cells divided into blocks, a command state machine decodes a refresh command entered, and sends a decoded result to a write state machine. The write state machine performs a refresh operation in accordance with the decoded result. The nonvolat
6006313 Semiconductor memory device that allows for reconfiguration around defective zones in a memory a December 21, 1999
An electrically rewritable nonvolatile semiconductor memory device made in accordance with a preferred embodiment of this invention, includes CAM data setting means for storing CAM data electrically written therein, wherein the CAM data is received from an external source; address fixing
6000004 Nonvolatile semiconductor memory device with write protect data settings for disabling erase fro December 7, 1999
A nonvolatile semiconductor memory device including: a memory cell array for storing data therein in a nonvolatile manner; block protect data storage regions provided for the respective blocks, for storing data therein in a nonvolatile manner; and block protect means for disabling an
5673222 Nonvolatile semiconductor memory device September 30, 1997
An electrically erasable and rewritable semiconductor memory device including at least one memory block, comprising: a WP signal generator for generating a WP signal for controlling protection of data stored in the memory block; a protect state setting section for setting a protect state
5619470 Non-volatile dynamic random access memory April 8, 1997
A memory device including a memory for storing data having volatile and non-volatile capability; an access circuit for reading/writing the data stored in a volatile state at an address in said memory in accordance with an access command indicating the address; a transfer circuit for
5488587 Non-volatile dynamic random access memory January 30, 1996
The presently claimed NVDRAM including: volatile memory cells which require a refreshing operation; non-volatile memory cells; an address generation circuit for automatically generating in sequence respective addresses; a self-refresh circuit; a refresh timing circuit; a self-store start
5414671 Semiconductor memory device having operation control means with data judging function May 9, 1995
In accordance with the levels of input signals, a recall signal or store signal is generated and held. Based on the signal currently held, only one of the read/write timing circuit, recall timing circuit and store timing circuit is enabled for operation with the operation of the other tw
5396461 Non-volatile dynamic random access memory device March 7, 1995
A non-volatile dynamic random access memory device which includes a memory section including at least non-volatile memory cells for a non-volatile mode operation which includes a recall operation and a store operation; and a rewriting device for rewriting data when the power is turned on
5381379 Non-volatile dynamic random access memory device; a page store device and a page recall device u January 10, 1995
An NVDRAM memory device which performs a recall operation in which non-volatile data stored in memory cell is converted to volatile data in a recall mode, a store operation in which the volatile data stored in the memory cell is converted to the non-volatile data in a store mode, and a
5287319 Nonvolatile semiconductor memory device February 15, 1994
In the normal selfrefresh mode, the timer output selection circuit selects the timer output of a longer cycle from the timer outputs generated by the internal timer circuit, and the selected timer output supplied as an operation activation signal for the selfrefresh operation. Using this
5181188 Semiconductor memory device January 19, 1993
A semiconductor memory device having memory cells in which a DRAM section and an EEPROM section are combined, and a transistor for transferring data between the DRAM and EEPROM sections is disclosed. The DRAM section includes a MOS transistor, and a capacitor one electrode of which is
5153853 Method and apparatus for measuring EEPROM threshold voltages in a nonvolatile DRAM memory device October 6, 1992
A method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell. The DRAM node of the NVDRUM cell is charged to a high potential and allowed to discharge through the EEPROM transistor. Since the gate of the EEPROM is
5146431 Method and apparatus for page recall of data in an nonvolatile DRAM memory device September 8, 1992
In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins

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