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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Fujishima; Kazuyasu
Address:
Hyogo, JP
No. of patents:
62
Patents:


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Patent Number Title Of Patent Date Issued
RE34463 Semiconductor memory device with active pull up November 30, 1993
A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC.
6859403 Semiconductor memory device capable of overcoming refresh disturb February 22, 2005
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6414883 Semiconductor memory device July 2, 2002
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6404056 Semiconductor integrated circuit June 11, 2002
On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interc
6272055 Semiconductor memory device August 7, 2001
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
6214664 Method of manufacturing semiconductor device April 10, 2001
In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and
6069379 Semiconductor device and method of manufacturing the same May 30, 2000
In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and
5969420 Semiconductor device comprising a plurality of interconnection patterns October 19, 1999
On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the intercon
5943273 Semiconductor memory device August 24, 1999
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
5687123 Semiconductor memory device November 11, 1997
Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The secon
5509132 Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and ope April 16, 1996
A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each
5504713 Semiconductor memory device with redundancy circuit April 2, 1996
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a
5461589 Bit line structure for semiconductor memory device with bank separation at cross-over regions October 24, 1995
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the resp
5416734 Bit line structure for semiconductor memory device May 16, 1995
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the resp
5371714 Method and apparatus for driving word line in block access memory December 6, 1994
In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifi
5353427 Semiconductor memory device for simple cache system with selective coupling of bit line pairs October 4, 1994
A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory
5321657 Random access memory of a CSL system with a bit line pair and an I/O line pair independently set June 14, 1994
In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, o
5315548 Column selecting circuit in semiconductor memory device May 24, 1994
Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals.
5289417 Semiconductor memory device with redundancy circuit February 22, 1994
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a
5283762 Semiconductor device containing voltage converting circuit and operating method thereof February 1, 1994
The semiconductor memory device contains a voltage converting circuit. The voltage converting circuit includes a plurality of reference voltage generating circuits for respectively generating a plurality of reference voltages at different levels. The voltage converting circuit further
5280443 Bit line structure for semiconductor memory device January 18, 1994
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the
5267214 Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory de November 30, 1993
A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to
5250458 Method for manufacturing semiconductor memory device having stacked memory capacitors October 5, 1993
A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner
5226147 Semiconductor memory device for simple cache system July 6, 1993
A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory
5222047 Method and apparatus for driving word line in block access memory June 22, 1993
In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifi
5214601 Bit line structure for semiconductor memory device including cross-points and multiple interconn May 25, 1993
A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective b
5189316 Stepdown voltage generator having active mode and standby mode February 23, 1993
In an active mode, a transistor 61 or 63 is turned on, so that a reference voltage generator circuit 1 and an internal voltage correcting circuit 2 are activated. Consequently, an internal voltage V.sub.INT which is stepped down is applied to an internal main circuit 7. Conversely, in a
5185744 Semiconductor memory device with test circuit February 9, 1993
A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding
5184327 Semiconductor memory device having on-chip test circuit and method for testing the same February 2, 1993
In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15 20). The output line (L) is provided with plu
5179687 Semiconductor memory device containing a cache and an operation method thereof January 12, 1993
A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive
5136543 Data descrambling in semiconductor memory device August 4, 1992
A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with comple
5111386 Cache contained type semiconductor memory device and operating method therefor May 5, 1992
A dynamic random access memory with a fast serial access mode for use in a simple cache system includes a plurality of memory cell blocks prepared by division of a memory cell array, a plurality of data latches each provided for each column in the memory cell blocks and a block selector.
5103426 Decoding circuit and method for functional block selection April 7, 1992
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to
5088063 Semiconductor memory device having on-chip test circuit February 11, 1992
In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15, 20). The output line (L) is provided with pl
5077688 Semiconductor memory device having improved memory cells provided with cylindrical type capacito December 31, 1991
A semiconductor memory device having a storage region constituted with the arrangement of a plurality of memory cells on a main surface of a semiconductor substrate. Each memory cell includes a switching element and a passive element for signal retention connected to the switching elemen
5060230 On chip semiconductor memory arbitrary pattern, parallel test apparatus and method October 22, 1991
An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (
5030586 Method for manufacturing semiconductor memory device having improved resistance to .alpha. parti July 9, 1991
In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type
5022007 Test signal generator for semiconductor integrated circuit memory and testing method thereof June 4, 1991
A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is
5014241 Dynamic semiconductor memory device having reduced soft error rate May 7, 1991
Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line.
5012447 Bit line structure for a dynamic type semiconductor memory device April 30, 1991
Each of the bit lines constituting each of a plurality of bit line pairs included in a portion of a memory cell array comprises even-numbered intersecting portions. At the intersecting portion, the materials of respective bit lines are different from each other. The bit lines are for
4980310 Method of making a trench dram cell December 25, 1990
A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the centra
4977542 Dynamic semiconductor memory device of a twisted bit line system having improved reliability of December 11, 1990
An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are
4972380 Decoding circuit for functional block November 20, 1990
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to
4953164 Cache memory system having error correcting circuit August 28, 1990
There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell arra
4926385 Semiconductor memory device with cache memory addressable by block within each column May 15, 1990
A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting cir
4918692 Automated error detection for multiple block memory array chip and correction thereof April 17, 1990
A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking
4914632 Semiconductor devices having redundancy circuitry and operating method therefor April 3, 1990
A plurality of word drivers are provided corresponding to a plurality of word lines. A switch band is provided between the plurality of word drivers and a plurality of row decoders. Each row decoder is connected to four word drivers through the switch band. The state of connection betwee
4914630 Refresh arrangement in a block divided memory including a plurality of shift registers April 3, 1990
In a block access memory, the memory cell array is divided into a plurality of blocks, one word line is selected based on the external address and the access to the memory cells connected thereto is carried out in one block and, simultaneously, one word line is selected based on the inte
4896297 Circuit for generating a boosted signal for a word line January 23, 1990
A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first pow
4890261 Variable word length circuit of semiconductor memory December 26, 1989
A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is group
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