| Patent Number |
Title Of Patent |
Date Issued |
| 7623450 |
Methods and apparatus for improving security while transmitting a data packet |
November 24, 2009 |
| In a first aspect, a first method of transmitting a data packet is provided. The first method includes the steps of (1) for each connection from which a data packet may be transmitted, storing header data corresponding to the connection; (2) employing a user application to form heade |
| 7606166 |
System and method for computing a blind checksum in a host ethernet adapter (HEA) |
October 20, 2009 |
| A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of |
| 7586936 |
Host Ethernet adapter for networking offload in server environment |
September 8, 2009 |
| An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ether |
| 7555002 |
Infiniband general services queue pair virtualization for multiple logical ports on a single phy |
June 30, 2009 |
| An aliased queue pair is provided within a logically partitioned data processing system for each logical partition for the single general services management queue pair that exists within a physical host channel adapter. Packets intended for the logical ports are received at the phys |
| 7552374 |
Apparatus and method for tracking packets in a reliably connected transmission system |
June 23, 2009 |
| A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data |
| 7492771 |
Method for performing a packet header lookup |
February 17, 2009 |
| A method for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The method includes providing a parser, providing a lookup engine coupled with the parser, and providing a processor coupled with the lookup engine. The parser is for parsing |
| 7475209 |
Moving hardware context structures in memory while maintaining system operation |
January 6, 2009 |
| An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired b |
| 7428598 |
Infiniband multicast operation in an LPAR environment |
September 23, 2008 |
| A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A pref |
| 7360140 |
Apparatus and method for tracking packets in a reliably connected transmission system |
April 15, 2008 |
| A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data |
| 7328390 |
Apparatus and method for tracking packets in a reliably connected transmission system |
February 5, 2008 |
| A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data |
| 7308539 |
Concurrent read access and exclusive write access to data in shared memory architecture |
December 11, 2007 |
| Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission to modify that block |
| 7283473 |
Apparatus, system and method for providing multiple logical channel adapters within a single phy |
October 16, 2007 |
| An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter |
| 7188198 |
Method for implementing dynamic virtual lane buffer reconfiguration |
March 6, 2007 |
| A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one secon |
| 7010633 |
Apparatus, system and method for controlling access to facilities based on usage classes |
March 7, 2006 |
| An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With t |
| 6938138 |
Method and apparatus for managing access to memory |
August 30, 2005 |
| A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being |
| 6920519 |
System and method for supporting access to multiple I/O hub nodes in a host bridge |
July 19, 2005 |
| Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to o |
| 6785759 |
System and method for sharing I/O address translation caching across multiple host bridges |
August 31, 2004 |
| A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a |
| 6601148 |
Infiniband memory windows management directly in hardware |
July 29, 2003 |
| A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A se |
| 6578122 |
Using an access key to protect and point to regions in windows for infiniband |
June 10, 2003 |
| A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate |
| 6529991 |
Ordering mechanism, ordering method and computer program product for implementing PCI peer to fu |
March 4, 2003 |
| An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read comm |
| 6275876 |
Specifying wrap register for storing memory address to store completion status of instruction to |
August 14, 2001 |
| A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address |
| 6260090 |
Circuit arrangement and method incorporating data buffer with priority-based data storage |
July 10, 2001 |
| A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a data buffer with a priority-based data storage capability to handle incoming data from a plurality of available data sources. With such a capability, different relative pri |
| 6185642 |
Bus for high frequency operation with backward compatibility and hot-plug ability |
February 6, 2001 |
| A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first |
