| Patent Number |
Title Of Patent |
Date Issued |
| 7583596 |
Priority scheduling using per-priority memory structures |
September 1, 2009 |
| A system schedules traffic flows on an output port using circular memory structures. The circular memory structures may include rate wheels that include a group of sequentially arranged slots. The traffic flows may be assigned to different rate wheels on a per-priority basis. |
| 7457247 |
Collision compensation in a scheduling system |
November 25, 2008 |
| A system schedules traffic flows on an output port using a circular memory structure. The circular memory structure may be a rate wheel that includes a group of sequentially arranged slots. The rate wheel schedules the traffic flows in select ones of the slots based on traffic shaping |
| 7046251 |
Editing system with router for connection to HDTV circuitry |
May 16, 2006 |
| A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality |
| 6961801 |
Method and apparatus for accessing video data in memory across flow-controlled interconnects |
November 1, 2005 |
| Command data may be embedded in the data transmitted over an interconnect between video devices to specify memory addresses in a destination device. Using an embedded address allows address-dependent data to be transmitted over the interconnect without losing these attributes. For exampl |
| 6678002 |
HDTV editing and effects previsualization using SDTV devices |
January 13, 2004 |
| A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high defini |
| 6407775 |
Image resizer and frame rate converter with pulldown controller |
June 18, 2002 |
| Film frames, or other images in which fields are captured at the same point in time, may be processed as a sequence of temporally coherent image fields or as progressive images. Such images may be obtained, for example, by digitizing signals from a telecine and dropping redundant fields |
| 6327253 |
Method and apparatus for controlling switching of connections among data processing devices |
December 4, 2001 |
| Multiple data processing devices may be interconnected through a switching mechanism while simultaneously conveying flow control information over the interconnect. Mechanisms are provided to ensure that the flow of data to and from interconnected devices has completed prior to changing t |
| 6304932 |
Queue-based predictive flow control mechanism with indirect determination of queue fullness |
October 16, 2001 |
| A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing |
| 6239815 |
Video data storage and transmission formats and apparatus and methods for processing video data |
May 29, 2001 |
| In order to efficiently use processing and transmission bandwidth and data storage of a computer system, video data is represented using integer and fractional values. The integer value has a precision defined by the precision of the data paths of the computer system. These integer and |
| 6229576 |
Editing system with router for connection to HDTV circuitry |
May 8, 2001 |
| A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality |
| 6226038 |
HDTV editing and effects previsualization using SDTV devices |
May 1, 2001 |
| A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high defini |
| 6182176 |
Queue-based predictive flow control mechanism |
January 30, 2001 |
| A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing |
| 6141691 |
Apparatus and method for controlling transfer of data between and processing of data by intercon |
October 31, 2000 |
| An interface enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls the flow of data between the processing elements. The flow control allows the processing elements to be data independent, i.e., the processing elements need |
| 6134607 |
Method and apparatus for controlling data flow between devices connected by a memory |
October 17, 2000 |
| A memory is used as a data buffer and switch between devices producing and consuming data in combination with a separate control channel which conveys flow control information between the devices connected through the memory. The control channel includes a signal sent from a sender to a |
| 6105083 |
Apparatus and method for controlling transfer of data between and processing of data by intercon |
August 15, 2000 |
| The present invention provides a generic interface which enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls flow of data between the processing elements. The flow control allows the processing elements to be data indepen |
| 5586274 |
Atomic operation control scheme |
December 17, 1996 |
| A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on |
| 5530933 |
Multiprocessor system for maintaining cache coherency by checking the coherency in the order of |
June 25, 1996 |
| A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitt |
